Results 241 to 250 of about 1,417 (268)
2018 New Generation of CAS (NGCAS), 2018 This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only
Hua Fan, Quanyuan Feng, Kelin Zhang
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An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5µm CMOS process and the active core area is 0.5*1.0 mm2. Measurement results show the A/D achieves 49.8dB peak
Fule Li
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2015 IEEE Custom Integrated Circuits Conference (CICC), 2015
Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs
Chris H Kim
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Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs
Chris H Kim
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0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC)
2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 2011This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted
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The Development of Successive Approximation Register for SAR ADC
2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon)Kristina D. Pepelyaeva +1 more
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Journal of Nanoelectronics and Optoelectronics, 2020
This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%.
Sheng-Biao An +4 more
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This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%.
Sheng-Biao An +4 more
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2017 International Conference on Circuits, System and Simulation (ICCSS), 2017
A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs.
Sounak Roy +3 more
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A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs.
Sounak Roy +3 more
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A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC
2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator
D. S. Shylu +2 more
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2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), 2017
A novel and reliable high-resolution and high-speed SAR ADC is presented in this paper. In the proposed article, a new compound R-2R/C structure is utilized in order to achieve both high-resolution and high-speed SAR ADC simultaneously. As simulation results verify that, at 1.8 V and 100 MS/s sampling rate with a Nyquist input, the ADC achieves an SNDR
Sina Mahdavi, Esmail Ghadimi
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A novel and reliable high-resolution and high-speed SAR ADC is presented in this paper. In the proposed article, a new compound R-2R/C structure is utilized in order to achieve both high-resolution and high-speed SAR ADC simultaneously. As simulation results verify that, at 1.8 V and 100 MS/s sampling rate with a Nyquist input, the ADC achieves an SNDR
Sina Mahdavi, Esmail Ghadimi
openaire +1 more source