Results 61 to 70 of about 4,246 (285)
Ternary Logic Dynamic CMOS Comparators [PDF]
In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low ...
Jun Biao Liu +4 more
core +1 more source
A reconfigurable logic‐in‐memory cell composed of triple‐gated feedback field‐effect transistors implements multiple combinational logic functions within a single configuration. By utilizing program gates as dynamic input terminals, the proposed cell performs full adder, full subtractor, 2‐to‐1 multiplexer, and 4‐to‐2 encoder operations without ...
Minhyeok Seol +5 more
wiley +1 more source
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
Bandgap‐engineered AlGaAs/GaAs heterostructures exhibit wavelength‐selective dual‐polarity photoelectrochemistry, switching from photocathodic to photoanodic response depending on excitation wavelength. The polarity transition is governed by band‐selective absorption, built‐in electric‐field‐driven carrier transport, and interfacial charge‐transfer ...
Yukai Mao +9 more
wiley +1 more source
One-Dimensional Lazy Quantum Walk in Ternary System
Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional lazy quantum walk in the ternary quantum domain and show its equivalence for circuit realization in ...
Amit Saha +3 more
doaj +1 more source
A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology
With the successful development of information technology, particularly in big data and neural network scopes, the appetency for denser memory compositions has exponentially outreached.
Aram Yousefi +2 more
doaj +1 more source
Ternary logic in parallel multipliers* [PDF]
The logic cost and speed of parallel multipliers implemented in both binary and ternary logic is studied. Binary operand lengths of 8 through 32 bits and the corresponding ternary digit range of 6 through 21 are considered.
Z. G. Vranesic, V. C. Hamacher
core
Ion‐Reconfigurable “N”‐Shaped Antiambipolar Behavior in Organic Electrochemical Transistors
A unique N‐shaped negative differential transconductance (NDT) characteristics is demonstrated in single‐polymer organic electrochemical transistors through a sequential doping–redox–doping process driven by iodide ions. This redox‐driven mechanism enables low‐voltage, ion‐controlled reconfigurability and tunable current modulation, allowing seamless ...
Debdatta Panigrahi +11 more
wiley +1 more source
Ultra low power design of multi-valued logic circuit for binary interfaces
From the dawn of the computer age, man has mass produced binary components for computers, due to which ternary or higher radix computers are not yet commercially used.
Mansi Jhamb, Ratnesh Mohan
doaj +1 more source
Delay-insensitive ternary logic (DITL) [PDF]
This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-
Parameswaran Nair, Ravi Sankar
core +1 more source

