Design and Application of Memristive Balanced Ternary Univariate Logic Circuit [PDF]
Micromachines, 2023 This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed.
Xiaoyuan Wang +4 more
doaj +4 more sources
Ternary Logic Design Based on Novel Tunneling-Drift-Diffusion Field-Effect Transistors [PDF]
NanomaterialsIn this paper, a novel Tunneling-Drift-Diffusion Field-Effect Transistor (TDDFET) based on the combination of the quantum tunneling and conventional drift-diffusion mechanisms is proposed for the design of ternary logic circuits. The working principle of
Bin Lu +7 more
doaj +2 more sources
Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors [PDF]
Nature Communications, 2022 High-density information processing without increasing the circuit complexity is highly desired in electronics. Here, Im et al. demonstrate a low-voltage organic ternary logic circuit vertically integrated with the nonvolatile flash memory, increasing ...
Junhwan Choi +7 more
doaj +2 more sources
Design of Ternary Logic and Arithmetic Circuits Using GNRFET [PDF]
IEEE Open Journal of Nanotechnology, 2020 Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits.
Zarin Tasnim Sandhie +2 more
doaj +2 more sources
Binary and ternary logic-in-memory using nanosheet feedback field-effect transistors with triple-gated structure [PDF]
Scientific ReportsIn this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p-
Jongseong Han +4 more
doaj +2 more sources
Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders [PDF]
E3S Web of Conferences, 2023 This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design.
C. Venkataiah +6 more
doaj +1 more source
Ternary combinational logic gate design based on tri-valued memristors
Frontiers in Physics, 2023 Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring.
Xiao-Jing Li +6 more
doaj +1 more source
Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits [PDF]
E3S Web of Conferences, 2023 Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits.
C. Venkataiah +6 more
doaj +1 more source
Design of ternary full-adder and full-subtractor using pseudo NCNTFETs
e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023 Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular.
SV RatanKumar +2 more
doaj +1 more source
Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
IEEE Access, 2021 Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded ...
Jihad Mohamed Aljaam +2 more
doaj +1 more source