Results 21 to 30 of about 1,093 (235)

Ternary combinational logic gate design based on tri-valued memristors

Frontiers in Physics, 2023
Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring.
Xiao-Jing Li, Xiao-Jing Li, Xiao-Yuan Wang, Xiao-Yuan Wang, Pu Li, Herbert H. C. Iu, Zhi-Qun Cheng   +6 more
doaj   +1 more source

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023
Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular.
SV RatanKumar, L Koteswara Rao, M Kiran Kumar   +2 more
doaj   +1 more source

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

IEEE Access, 2021
Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded ...
Jihad Mohamed Aljaam, Ramzi A. Jaber, Somaya Ali Al-Maadeed   +2 more
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Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”

IEEE Access, 2020
In the above article [1], R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued ...
Daniel Etiemble
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One-Dimensional Lazy Quantum Walk in Ternary System

IEEE Transactions on Quantum Engineering, 2021
Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional lazy quantum walk in the ternary quantum domain and show its equivalence for circuit realization in ...
Amit Saha, Sudhindu Bikash Mandal, Debasri Saha, Amlan Chakrabarti   +3 more
doaj   +1 more source

Carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) based ternary combinational logic circuits [PDF]

, 2021
The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems.
Chia Yee Ooi, Mohd Nawi, Illani, Illani Mohd Nawi, Mohd. Nawi, llani, Ooi, Chia Yee, Fawnizu Azmadi Hussin, Ahmad, Mohamad Radzi, Mohamad Radzi Ahmad, Furqan Zahoor, Farooq Ahmad Khanday, Rokhani, Fakhrul Zaman, Chia, Yee Ooi, Khanday, Farooq Ahmad, Zahoor, Furqan, Hussin, Fawnizu Azmadi, Ahmad Khanday, Farooq, Fakhrul Zaman Rokhani   +16 more
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Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

, 2020
Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect ...
Seokhyeong Kang, Yongsu Lee, Byoung Hun Lee, Kim, Kiyung, Kim, Daeyeon, Kim, So-Young, Kiyung Kim, Lee, Byoung Hun, Sunmean Kim, So-Young Kim, Lee, Yongsu, Kim, Sunmean, Kang, Seokhyeong, Daeyeon Kim   +13 more
core   +1 more source

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)

Micromachines, 2021
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated.
Furqan Zahoor, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad, Illani Mohd Nawi   +4 more
doaj   +1 more source

From static ternary adders to high-performance race-free dynamic ones

The Journal of Engineering, 2015
This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic.
Shirin Rezaie, Reza Faghih Mirzaee, Keivan Navi, Keivan Navi, Omid Hashemipour   +4 more
doaj   +1 more source

Static Timing Analysis for Critical Path Identification in Ternary Logic Circuits

Iranian Journal of Electrical and Electronic Engineering, 2022
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers.
S. Abolmaali
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