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Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”
In the above article [1], R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued ...
Daniel Etiemble
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With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical ...
Mingqiang Huang +4 more
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One-Dimensional Lazy Quantum Walk in Ternary System
Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional lazy quantum walk in the ternary quantum domain and show its equivalence for circuit realization in ...
Amit Saha +3 more
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New ternary decoders using hybrid memristor-MOS logic [PDF]
Integrating memristor technology with traditional CMOS has led to innovative designs for ternary logic, significantly enhancing the performance and efficiency of digital integrated circuits.
Ramesh Kumar, Bal Chand Nagar
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Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated.
Furqan Zahoor +4 more
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From static ternary adders to high-performance race-free dynamic ones
This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic.
Shirin Rezaie +4 more
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Transistor-tunnel-diode ternary-logic circuits
Two new basic circuits for ternary-logical operations are described. Analogue simulation and experimental measurements confirm that the switching speeds of the ternary circuits can be comparable with those in similar binary circuits. It is concluded that a marginal improvement in processing rate may be achieved with ternary logic using transistor ...
W.D. Ryan, H. Madany
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Static Timing Analysis for Critical Path Identification in Ternary Logic Circuits
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers.
S. Abolmaali
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Design of ternary logic gates and circuits using GNRFETs [PDF]
In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects.
Badugu Divya Madhuri +1 more
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In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed.
Furqan Zahoor +3 more
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