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Design of encoder for ternary logic circuits
2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2012Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented.
P Viswa Saidutt +3 more
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An Efficient Approach to Design Ternary Logic Circuits with GNRFETs
2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS)This project introduces a novel approach for designing ternary logic circuits using Graphene Nanoribbon Field-Effect Transistors (GNRFETs) and HSPICE software.
P. V. Ramana +4 more
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Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2018Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer.
C. Vudadha +3 more
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Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits
IEEE transactions on nanotechnology, 2022The quest for efficient technologies beyond the traditional CMOS (Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor).
Sharvani Gadgil, C. Vudadha
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Swhched-current CMOS ternary logic circuits
International Journal of Electronics, 1995Abstract A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulations. The results obtained indicate that the proposed circuits have good noise margins of about 15% of the power supply voltage ...
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Pseudo-random testing of CMOS ternary logic circuits
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988Two structures that can be used to test ternary logic VLSI circuits are described and compared: the ternary BILBO (built-in logic block observer) and the ternary CALBO (cellular automaton logic block observer). These structures can be used to generate pseudorandom test patterns and signatures.
C. Rozon, H.T. Mouftah
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A Review on Fundamentals of Ternary Reversible Logic Circuits
2020 International Conference on Computational Performance Evaluation (ComPE), 2020One of the main motivations for using ternary logic systems is the amount of information per circuit line is higher as compared to the corresponding binary logic representation, thereby leading to more compact circuit realizations. This is particularly attractive for quantum computing as qutrits are expensive resources and minimizing their number is ...
P. Mercy Nesa Rani +1 more
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A novel ternary logic circuit using Josephson junction
IEEE Transactions on Magnetics, 1989A novel Josephson complementary ternary logic (JCTL) circuit is described. This fundamental circuit is based on the combination of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive direction and the other in the negative direction.
M. Morisue, K. Oochi, M. Nishizawa
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Ternary logic circuit design based on single electron transistors
Journal of Semiconductors, 2009Based on the I–V characteristics and the function of adjustable threshold voltage of a single electron transistor (SET), we design the basic ternary logic circuits, which have been simulated by SPICE and their power and transient characteristics have been extensively analyzed. The simulation results indicate that the proposed circuits exhibit a simpler
Wu Gang, Cai Li, Li Qin
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A GNRFET-based Approach to Design Ternary Logic Arithmetic Circuits
2025 5th International Conference on Soft Computing for Security Applications (ICSCSA)To drive the need for higher density, faster processing and improved energy efficiency beyond the limitations of binary logic, researchers are exploring ternary logic (using states 0, 1, and 2, respectively).
Dudyala Devika +5 more
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