Results 231 to 240 of about 853 (244)
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CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
IEEE Nanotechnology Magazine, 2011Yong-Bin Kim +2 more
exaly
Design of Ternary Logic Circuits Using CNFETs
2018Chetan Vudadha, M. B. Srinivas
openaire +1 more source
Design and Synthesis of Ternary CMOS Logic Circuits and D-Element
IEEJ Transactions on Industry Applications, 2019Chikatoshi Yamada, Yasunori Nagata
exaly
Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits
Journal of VLSI circuits and systems, 2023openaire +1 more source
An Efficient Approach to Design Ternary Logic Circuits with GNRFETs
2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS)P. Venkat Ramana +4 more
openaire +1 more source
Design of Adder Circuits using GNRFETs in Ternary Logic
2025 7th International Conference on Intelligent Sustainable Systems (ICISS)Harivaram Shervani +5 more
openaire +1 more source

