Results 211 to 220 of about 1,093 (235)
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Functionalized Organic Material Platform for Realization of Ternary Logic Circuit
ACS Applied Materials & Interfaces, 2020Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required ...
Jaeho Jeon +8 more
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Design of ternary logic circuits using CNTFET
2018 International Symposium on Devices, Circuits and Systems (ISDCS), 2018The work in this paper presents the design of ternary logic circuits using MOSFET-like carbon nanotube field effect transistor (CNTFET). The ternary logic is one of multivalued logic circuits which is the best substitute for traditional binary logic because of its low power consumption and low power delay product (PDP) resulting from reduced complexity
Debaprasad Das +2 more
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A design of ternary logic circuits using M‐NAND and NOT gates
Systems and Computers in Japan, 1985AbstractWe have proposed the canonical form for the p‐valued logical function (p is a natural number, p > 2), using M‐AND, M‐OR and NOT operations. However, the relations among those operations have been discussed only briefly. This paper discusses in detail the properties of M‐NAND, M‐OR and NOT operations for the ternary case (p = 3), deriving ...
Akio Odaka, Kunio Satoh
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Redundant algebra and integrated circuit implementation of ternary logic and their applications
1993 IEEE International Symposium on Circuits and Systems, 2002A new algebra called redundant algebra is proposed and analyzed for the design of the ternary logic systems. The ternary systems can be realized by dynamic CMOS logic circuits. A new dynamic differential logic called CMOS redundant differential logic (CRDL) is developed to increase the logic flexibility and the circuit performance.
Hong-Yi Huang, Chung-Yu Wu
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Swhched-current CMOS ternary logic circuits
International Journal of Electronics, 1995Abstract A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulations. The results obtained indicate that the proposed circuits have good noise margins of about 15% of the power supply voltage ...
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An Efficient Design Methodology for CNFET Based Ternary Logic Circuits
2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016Ternary logic is a promising alternative to conventional binary logic. Implementation of ternary logic circuits however requires devices with multiple thresholds, which is a complex task with current CMOS technology. Carbon Nanotube based FETs (CNFETs) present an easier alternative for the implementation of ternary logic circuits since their threshold ...
Chetan Kumar Vudadha +2 more
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Self-checking binary logic systems using ternary logic circuits
Canadian Electrical Engineering Journal, 1984The present status of multivalued logic is highlighted in a Canadian context. A particular example is given of the use of ternary circuits in the solution of the problem of testability of binary logic, through the introduction of a new concept called 2-of-3-valued logic.
M. Hu, K. C. Smith
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Design and novel approach for ternary and quaternary logic circuits
2017 2nd International Conference for Convergence in Technology (I2CT), 2017At beginning era of digital design, the binary logic is used in all industrial applications. The binary logic uses 2 states i.e. 0's and 1's to represent each state. Since the binary logic uses 2 states, it requires more number of bits to represent a number. For example, the number 25 is represented in (11001) 2 this format. So this number 25 requires
R.N. Uma Mahesh, J. Sudeep
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Pseudo-random testing of CMOS ternary logic circuits
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988Two structures that can be used to test ternary logic VLSI circuits are described and compared: the ternary BILBO (built-in logic block observer) and the ternary CALBO (cellular automaton logic block observer). These structures can be used to generate pseudorandom test patterns and signatures.
C. Rozon, H.T. Mouftah
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Ternary logic circuit for error detection and error correction
Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic, 2003The binary logic system formed by a ternary logic circuit has error-detecting and error-correcting functions. A three-valued polar code and a ternary-logic error-detecting and error-correcting circuit for the data transmission system are presented.
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