Results 211 to 220 of about 853 (244)

Design of encoder for ternary logic circuits

2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2012
Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented.
P Viswa Saidutt, V Srinivas, P Sai Phaneendra, N Moorthy Muthukrishnan   +3 more
openaire   +1 more source

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate.
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang   +3 more
openaire   +1 more source

A useful application of CMOS ternary logic to the realisation of asynchronous circuits

Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002
This paper shows how the application of a CMOS ternary logic is useful in the realisation of delay insensitive (DI) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface.
Mariani R., RONCELLA, ROBERTO, SALETTI, ROBERTO, TERRENI, PIERANGELO   +3 more
openaire   +2 more sources

A Review on Fundamentals of Ternary Reversible Logic Circuits

2020 International Conference on Computational Performance Evaluation (ComPE), 2020
One of the main motivations for using ternary logic systems is the amount of information per circuit line is higher as compared to the corresponding binary logic representation, thereby leading to more compact circuit realizations. This is particularly attractive for quantum computing as qutrits are expensive resources and minimizing their number is ...
P. Mercy Nesa Rani, Phrangboklang Lyngton Thangkhiew   +1 more
openaire   +1 more source

On the realisation of delay-insensitive asynchronous circuits with CMOS ternary logic

Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2002
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described. The main advantage of ternary logic is the easy realisation of a handshake protocol that significantly reduces the communication requirement, one of the major drawback of asynchronous logic.
Mariani R., RONCELLA, ROBERTO, SALETTI, ROBERTO, TERRENI, PIERANGELO   +3 more
openaire   +2 more sources

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit

ACS Applied Materials & Interfaces, 2020
Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required ...
Jaeho Jeon, Min Je Kim, Gicheol Shin, Myeongjae Lee, Young Jae Kim, BongSoo Kim, Yoonmyung Lee, Jeong Ho Cho, Sungjoo Lee   +8 more
openaire   +3 more sources

JCTL: a Josephson complementary ternary logic circuit

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988
A novel complementary ternary logic circuit using Josephson junctions as switching gates is described. The principle of the circuit is based on the tristate of a Josephson junction, that is the state of switching in either positive direction or negative direction, in addition to the state of no switching.
M. Morisue, K. Ochi, M. Nishizawa
openaire   +1 more source

Design of ternary logic circuits using CNTFET

2018 International Symposium on Devices, Circuits and Systems (ISDCS), 2018
The work in this paper presents the design of ternary logic circuits using MOSFET-like carbon nanotube field effect transistor (CNTFET). The ternary logic is one of multivalued logic circuits which is the best substitute for traditional binary logic because of its low power consumption and low power delay product (PDP) resulting from reduced complexity
Debaprasad Das, Anirban Banerjee, Vikash Prasad   +2 more
openaire   +1 more source

Redundant algebra and integrated circuit implementation of ternary logic and their applications

1993 IEEE International Symposium on Circuits and Systems, 2002
A new algebra called redundant algebra is proposed and analyzed for the design of the ternary logic systems. The ternary systems can be realized by dynamic CMOS logic circuits. A new dynamic differential logic called CMOS redundant differential logic (CRDL) is developed to increase the logic flexibility and the circuit performance.
Hong-Yi Huang, Chung-Yu Wu
openaire   +1 more source

A design of ternary logic circuits using M‐NAND and NOT gates

Systems and Computers in Japan, 1985
AbstractWe have proposed the canonical form for the p‐valued logical function (p is a natural number, p > 2), using M‐AND, M‐OR and NOT operations. However, the relations among those operations have been discussed only briefly. This paper discusses in detail the properties of M‐NAND, M‐OR and NOT operations for the ternary case (p = 3), deriving ...
Akio Odaka, Kunio Satoh
openaire   +1 more source