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A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value ...
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We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously.
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Synthesis of ternary non-reversible logic circuits
IEEE Congress on Evolutionary Computation, 2010Reversible quantum circuits are a necessary subclass of quantum computation and its realization is required for any quantum computer to be universal. This paper investigates how to synthesis of arbitrary ternary non-reversible logic circuits by adding inputs with constant value and garbage outputs. Group theory has been also used to solve the synthesis
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Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms
IEEE Transactions on Emerging Topics in ComputingMulti-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems. However, the basic construction method for MVL circuit standard cells and the CMOS fabrication possibility/compatibility issues are still to be addressed.
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