Results 191 to 200 of about 1,093 (235)
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value ...
Seong-Jin Kim +2 more
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Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019 We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate.
Sunmean Kim +3 more
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Ternary circuits for Null Convention Logic
The 2011 International Conference on Computer Engineering & Systems, 2011 Null Convention Logic (NCL) adds a control value (NULL i.e., DATA not valid) to its Boolean set to create a symbolically complete logic system that is inherently self determined, locally autonomous, self synchronizing and delay insensitive. NCL circuits typically employ a dual-rail binary scheme to represent these three levels.
Sameh Andrawes, Paul Beckett
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IEE Proceedings, Part G: Circuits, Devices and Systems, 1990
We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously.
X W Wu
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We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously.
X W Wu
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Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms
IEEE Transactions on Emerging Topics in ComputingMulti-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems. However, the basic construction method for MVL circuit standard cells and the CMOS fabrication possibility/compatibility issues are still to be addressed.
Guangchao Zhao +2 more
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Synthesis of ternary non-reversible logic circuits
IEEE Congress on Evolutionary Computation, 2010Reversible quantum circuits are a necessary subclass of quantum computation and its realization is required for any quantum computer to be universal. This paper investigates how to synthesis of arbitrary ternary non-reversible logic circuits by adding inputs with constant value and garbage outputs. Group theory has been also used to solve the synthesis
Guowu Yang
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Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present
Chetan Vudadha +2 more
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A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed.
B Srinivasu, K Sridharan
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Design of Ternary Logic Circuits Using GNRFET and RRAM
Circuits, Systems, and Signal Processing, 2023Shaik Javid Basha, P Venkatramana
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A review on the design of ternary logic circuits*
Chinese Physics B, 2021A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits.
Xiao-Yuan Wang +3 more
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