Results 201 to 210 of about 1,093 (235)

Design Methodologies for Ternary Logic Circuits

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 2018
Ternary logic has advantage over binary circuits with respect to area and interconnect complexity. CNFET technology is ideal to implement ternary logic circuits because the threshold voltage of CNFETs depends on the physical dimensions of their channel. This work presents new approach to design CNFET-based ternary logic circuits. This approach uses 2:1
Chetan Kumar Vudadha, M. B. Srinivas
openaire   +1 more source

Combinational logical circuits into ternary logic

SPIE Proceedings, 2009
In this paper the authors present, from theoretical point of view combinational logical circuits achieved with optical devices that work using a ternary logic. Those three levels are clearly distinct and the danger of confusion does not exist. These models can be implemented not only in the integrated optics but also in the classic optics where the ...
Vasile Degeratu, Ştefania Degeratu, Paul Şchiopu, Carmen Şchiopu   +3 more
openaire   +1 more source

Logical Design of Ternary Switching Circuits

IEEE Transactions on Electronic Computers, 1965
A logical design theory for ternary voltage switching circuits is developed. The theory is based on familiar binary switching circuit elements and simplification methods. The theory thus leads to simple electronic realization. The basic system of ternary switching elements consists of function realizable by means of either diode gates or a single ...
Michael Yoeli, G. Rosenfeld
openaire   +1 more source

Synthesis of Balanced Ternary Reversible Logic Circuit

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013
Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2.
Bikromadittya Mondal, Pradyut Sarkar, Pranay Kumar Saha, Susanta Chakraborty   +3 more
openaire   +1 more source

Semiconductor circuits for ternary logic

Proceedings of the IEE Part C: Monographs, 1962
The advantages that can be obtained from using a ternary or higher-order system are enumerated. The various techniques using semiconductor, devices are described with particular reference to the ternary system, and the circuits that have been developed from these techniques are reviewed. The prototype circuits described in the paper have been developed
R.P. Hallworth, F.G. Heath
openaire   +1 more source

Design of encoder for ternary logic circuits

2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2012
Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented.
P Viswa Saidutt, V Srinivas, P Sai Phaneendra, N Moorthy Muthukrishnan   +3 more
openaire   +1 more source

A Review on Fundamentals of Ternary Reversible Logic Circuits

2020 International Conference on Computational Performance Evaluation (ComPE), 2020
One of the main motivations for using ternary logic systems is the amount of information per circuit line is higher as compared to the corresponding binary logic representation, thereby leading to more compact circuit realizations. This is particularly attractive for quantum computing as qutrits are expensive resources and minimizing their number is ...
P. Mercy Nesa Rani, Phrangboklang Lyngton Thangkhiew   +1 more
openaire   +1 more source

A useful application of CMOS ternary logic to the realisation of asynchronous circuits

Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002
This paper shows how the application of a CMOS ternary logic is useful in the realisation of delay insensitive (DI) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface.
Mariani R., RONCELLA, ROBERTO, SALETTI, ROBERTO, TERRENI, PIERANGELO   +3 more
openaire   +2 more sources

On the realisation of delay-insensitive asynchronous circuits with CMOS ternary logic

Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2002
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described. The main advantage of ternary logic is the easy realisation of a handshake protocol that significantly reduces the communication requirement, one of the major drawback of asynchronous logic.
Mariani R., RONCELLA, ROBERTO, SALETTI, ROBERTO, TERRENI, PIERANGELO   +3 more
openaire   +2 more sources

JCTL: a Josephson complementary ternary logic circuit

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988
A novel complementary ternary logic circuit using Josephson junctions as switching gates is described. The principle of the circuit is based on the tristate of a Josephson junction, that is the state of switching in either positive direction or negative direction, in addition to the state of no switching.
M. Morisue, K. Ochi, M. Nishizawa
openaire   +1 more source