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A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed.
Sridharan K, B Srinivasu
exaly   +2 more sources

Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present
Chetan Kumar Vudadha   +2 more
exaly   +2 more sources

Design of Ternary Logic Circuits Using GNRFET and RRAM

Circuits, Systems, and Signal Processing, 2023
P V Ramana, Javid Basha
exaly   +2 more sources

A review on the design of ternary logic circuits*

Chinese Physics B, 2021
A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits.
Xiao-Yuan Wang   +3 more
openaire   +1 more source

Logical Design of Ternary Switching Circuits

IEEE Transactions on Electronic Computers, 1965
A logical design theory for ternary voltage switching circuits is developed. The theory is based on familiar binary switching circuit elements and simplification methods. The theory thus leads to simple electronic realization. The basic system of ternary switching elements consists of function realizable by means of either diode gates or a single ...
Michael Yoeli, G. Rosenfeld
openaire   +1 more source

Design Methodologies for Ternary Logic Circuits

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 2018
Ternary logic has advantage over binary circuits with respect to area and interconnect complexity. CNFET technology is ideal to implement ternary logic circuits because the threshold voltage of CNFETs depends on the physical dimensions of their channel. This work presents new approach to design CNFET-based ternary logic circuits. This approach uses 2:1
Chetan Kumar Vudadha, M. B. Srinivas
openaire   +1 more source

Combinational logical circuits into ternary logic

SPIE Proceedings, 2009
In this paper the authors present, from theoretical point of view combinational logical circuits achieved with optical devices that work using a ternary logic. Those three levels are clearly distinct and the danger of confusion does not exist. These models can be implemented not only in the integrated optics but also in the classic optics where the ...
Vasile Degeratu   +3 more
openaire   +1 more source

Semiconductor circuits for ternary logic

Proceedings of the IEE Part C: Monographs, 1962
The advantages that can be obtained from using a ternary or higher-order system are enumerated. The various techniques using semiconductor, devices are described with particular reference to the ternary system, and the circuits that have been developed from these techniques are reviewed. The prototype circuits described in the paper have been developed
R.P. Hallworth, F.G. Heath
openaire   +1 more source

Synthesis of Balanced Ternary Reversible Logic Circuit

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013
Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2.
Bikromadittya Mondal   +3 more
openaire   +1 more source

Ternary circuits for Null Convention Logic

The 2011 International Conference on Computer Engineering & Systems, 2011
Null Convention Logic (NCL) adds a control value (NULL i.e., DATA not valid) to its Boolean set to create a symbolically complete logic system that is inherently self determined, locally autonomous, self synchronizing and delay insensitive. NCL circuits typically employ a dual-rail binary scheme to represent these three levels.
Sameh Andrawes, Paul Beckett
openaire   +1 more source

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