Results 251 to 260 of about 84,742 (270)

2:1 Multiplexer based design for ternary logic circuits

2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013
This paper presents a design methodology using multiplexers to implement any ternary logic function with carbon nanotube field effect transistors (CNFETs). Ternary logic is one of the promising alternatives to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects
Chetan Vudadha, Sowmya Katragadda, P Sai Phaneendra   +2 more
openaire   +1 more source

An Effective Method to Develop Pseudo Ntype-GNRFETs based Digital Circuits in Ternary Logic

International Conference on Computing Communication and Networking Technologies
Ternary logic systems are predominantly intriguing for nano-scaling design because of various advantages, including increased density and faster operation which may be accomplished with emerging technologies.
P. R. Ramaiah, Shaik Javid Basha, K. V. Kumar, Y. M. Rao   +3 more
semanticscholar   +1 more source

High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations.
Wanting Wen, Guangchao Zhao, Wanbo Hu, Ziye Li, Xingli Wang, Eby G. Friedman, B. Tay, Shaolin Ke, Mingqiang Huang   +8 more
semanticscholar   +1 more source

Null Convention Logic Circuits Using Balanced Ternary on SOI

2012
We propose and analyze novel Ternary logic circuits targeting an asynchronous Null Convention Logic (NCL) pipeline where the Null value (i.e. Data not valid) is used to make the pipeline self-synchronizing and delay insensitive. A balanced Ternary logic system is used, in which the logic set {High Data, Null, Low Data} maps to voltage levels {+VDD, 0V,
Sameh Andrawes, Paul Beckett
openaire   +1 more source

Memristor Emulator-Based Ternary Logic Gates for AI and Neuromorphic Hardware

2025 IEEE International Conference on Intelligent Signal Processing and Effective Communication Technologies (INSPECT)
This article explores the developing of logic gates using a memristor circuit utilizing the ternary logic concept that plays a pivotal role in enabling the hardware implementation of complex ternary neural circuits.
Gouranga Mandal, Mourina Ghosh, Pulak Mondal   +2 more
semanticscholar   +1 more source

Logic circuits based on ternary parametrons

Soviet Radiophysics, 1966
V. P. Komolov, A. S. Roshal
openaire   +1 more source

Cntfet-Based Logical and Arithmetic Circuits in Unbalanced Ternary Logic

2023
Shams Ul Haq, Vijay Kumar Sharma
openaire   +1 more source

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

AEU - International Journal of Electronics and Communications, 2023
Tabassum Khurshid, Vikram Singh
semanticscholar   +1 more source

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2017
S. M. I. B. Srinivasu, S. M. I. K. Sridharan   +1 more
semanticscholar   +1 more source

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

J. Circuits Syst. Comput., 2023
Tabassum Khurshid, Vikram Singh
semanticscholar   +1 more source