Results 61 to 70 of about 1,093 (235)

Molecularly Engineered Wing‐Shaped Azobenzene Memristors for Logic‐in‐Memory and Edge Visual Intelligence

Advanced Science, EarlyView.
Rational engineering of terminal substituents in symmetric azobenzene‐based molecules enables precise control over conformationally coupled charge‐transfer processes. This design yields tunable nonvolatile resistive memory behaviors, ranging from write‐once‐read‐many‐times (WORM) to rewritable switching.
Yanze Liu, Tao Han, Jiahui Ding, Hong Lian, Lingling Yao, Zhaoxin Xu, Xingyu Zhang, Shuanglong Wang, Jiangnan Xia, Tianchi Zhang, Weiwei Kang, Qingchen Dong   +11 more
wiley   +1 more source

A balanced Memristor-CMOS ternary logic family and its application

, 2023
The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified by simulation,
Iu, Herbert Ho-Ching, Elliman, Robert G., Dong, Chuan-Tao, Chen, Xin-Hui, Kang, Sung-Mo, Wang, Xiao-Yuan, Zhou, Jia-Wei, Nandi, Sanjoy Kumar   +7 more
core  

Intrinsic Dual‐Phase Regulated GeSe2 Nanoparticles Triggered by Ball‐Milling Treatment for Photonic Multi‐Valued Logic Circuits

Advanced Science, EarlyView.
We report the solid‐state ball milling, a traditional, reliable, mass‐productive material processing, to prepare the air‐stable and dual‐phase GeSe2‐x nanoparticles with extended photodetection feasibility toward optical‐wavelength regions. We further display photonic multi‐valued logic (MVL) circuit through the employment of a hybrid PMMA/GeSe2‐x ...
An‐Ting Tsai, Chun‐Jen Wang, Pin‐Chao Liao, Chin Shan Lue, Chia‐Nung Kuo, Le Vo Phuong Thuan, Po‐Hsuan Hsiao, Chang‐Hyun Kim, Chia‐Yun Chen   +8 more
wiley   +1 more source

Implementation and Applications of a Ternary Threshold Logic Gate

, 2022
Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node.
Ünsalan, Cem, Unutulmaz, Ahmet
core  

Reliably In‐Memory Ternary Stateful Logic Computing Based on Tri‐State Memristors with High On/Off Ratio

Advanced Electronic Materials
To surpass the slowdown of Moore's Law, multi‐valued logic (MVL) systems are explored to increase information processing density and enhance computational efficiency. Although conventional MVL systems offer substantial reductions in the number of devices
Junqi You, Yihong Hu, Dongliang Yang, Yinan Lin, Weifan Meng, Nuo Xu, Linfeng Sun   +6 more
doaj   +1 more source

Design and Simulation of Balanced Ternary Priority Encoder

Memories - Materials, Devices, Circuits and Systems
The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions ...
Aadarsh Ganesh Goenka, Shyamali Mitra, Harsh Maheshwari, Nibaran Das   +3 more
doaj   +1 more source

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

Advanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits

, 2017
We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits.
Sunhae Shin, Jeong, Jae Won, Kyung Rok Kim, Esan Jang, Jae Won Jeong, Shin, Sunhae, Kim, Kyung Rok, Jang, Esan   +7 more
core   +1 more source

Aging and Electrical Stability of DNTT Honey‐Gated OFETs

Advanced Electronic Materials, EarlyView.
DNTT honey‐gated organic transistors were fabricated and evaluated to assess short‐ and long‐term stability under electrical stress and aging. Short‐term transfer measurements (five days, 40 sweeps/day) showed minimal parameter shift, while extended measurements revealed gradual degradation over weeks.
Douglas H. Vieira, Ana C. de Paula, José D. F. Dias, Maria H. L. O. Fung, Rafael Furlan de Oliveira, Gabriel L. Nogueira, Keli F. Seidel, José P. M. Serbena, Neri Alves   +8 more
wiley   +1 more source

Design and Analysis the Performance of Ternary Logic Gates using Doping-Less FET [PDF]

ITM Web of Conferences
This paper presents the analysis of performance and design of ternary logic gates using doping- less field-effect transistors (DLFET) integrated with resistive memory (RM).
Prabu Arulraj Simon, A K Adharsh, Caleb Jebaseelan E Aaron   +2 more
doaj   +1 more source