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Self-checking binary logic systems using ternary logic circuits

Canadian Electrical Engineering Journal, 1984
The present status of multivalued logic is highlighted in a Canadian context. A particular example is given of the use of ternary circuits in the solution of the problem of testability of binary logic, through the introduction of a new concept called 2-of-3-valued logic.
M. Hu, K. C. Smith
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Logic synthesis of controllers for B-ternary asynchronous systems

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), 2002
Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case.
Y. Nagata, D.M. Miller, M. Mukaidono
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Experimental system of ternary logic optical computer with reconfigurability

SPIE Proceedings, 2009
An experimental system of a ternary logic optical computer, including its working principle, architecture and main components, is proposed. The main object of this paper is to give readers a holistic understanding of the ternary optical computer. This experimental system, which fully exploits the parallelism of optics, can have huge data bus width ...
Zhang-Yi Shen, Yi Jin, Jun-Jie Peng
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Ternary simulation of digital systems in CAD programmable logic

Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2003
Here is considered the problems of interpretative and compilation simulation of digital systems. Investigated the influence of logic transformation of gate models. Offered procedures, which modify the method of ternary simulation and avoid incorrect execution of direct implication in the cubic coverage of the given gate structure. Here is some examples,
A.S. Shkil, V.V. Pobezenko, I.Y. Sysenko
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A redundant binary adder using a symmetric ternary logic system

International Journal of Electronics, 1993
A construction method is described for a fast parallel adder by using a redundant binary code (RBC). The RBC used has a fixed radix 2 and a digit set {−1,0,1}. The fast parallel adder is composed of ternary-valued CMOS gate networks, which are used in the symmetric ternary logic system, and its construction can be optimized with them.
SHINSAKU HIGASHI   +3 more
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Comparative Analysis of Crosstalk Effects in Dielectric Inserted Horizontal andVertical Multi-layer GNR Interconnects for Ternary Logic System

ECS Journal of Solid State Science and Technology, 2022
In this work, the performance of copper (Cu), dielectric inserted horizontal graphene nanoribbon (Di-HGNR) interconnect and dielectric inserted vertical graphene nanoribbon (Di-VGNR) interconnects are investigated using active shielding and passive shielding techniques.
Gurijala Deepthi, Madhavi Tatineni
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