Results 141 to 150 of about 24,777 (278)
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Clues for glues: from serendipity to nature's blueprints in degrader discovery. [PDF]
Kozicka Z.
europepmc +1 more source
Chat computational fluid dynamics (CFD) introduces an large language model (LLM)‐driven agent that automates OpenFOAM simulations end‐to‐end, attaining 82.1% execution success and 68.12% physical fidelity across 315 benchmarks—far surpassing prior systems.
E Fan +8 more
wiley +1 more source
Reconfigurable binary and ternary logic devices enabling logic state modulation. [PDF]
Kwon YA +5 more
europepmc +1 more source
A New Moduli Set for Residue Number System in Ternary Valued Logic
M. Hosseinzad, K. Navi
openaire +1 more source
This review explores how shape‐changing structures—origami, bistable, and laminate structures—enable multifunctionality in soft robotics and metamaterials. Starting from structural design, it examines core principles, real‐world applications, and ongoing challenges.
Lingchen Kong, Yaoyao Fiona Zhao
wiley +1 more source
Energy-efficient design of CNTFET-based quaternary arithmetic circuits. [PDF]
Rupani A, Bansal D, Sharma K.
europepmc +1 more source
A charge‐domain ternary content‐addressable memory using one capacitor one nanoelectromechanical memory switch (1C‐1N TCAM) is proposed for energy‐efficient, high‐reliability computations. Integrated with the back‐end‐of‐line process, the 1C‐1N TCAM leverages the air gap capacitance to achieve a high capacitance ratio and ternary functionality.
Jin Wook Lee +5 more
wiley +1 more source
Design and optimization of a quaternary booth multiplier in quaternary logic using carbon nanotube transistors. [PDF]
Toosanloo SA, Javidan J.
europepmc +1 more source
A fully integrated analog processing‐in‐memory system is demonstrated, combining charge‐trap flash synapse arrays with a successive integration‐and‐rescaling neuron circuit. The architecture performs bit‐sliced analog accumulation with high linearity and low power, achieving efficient and scalable analog in‐memory computing and bridging device‐level ...
Sojoong Kim +4 more
wiley +1 more source

