Results 151 to 160 of about 10,498 (226)

Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

Physica Scripta, 2023
To improve the DC and analog/HF performance, a novel dual line tunneling based TFET (DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript.
Tammisetti Ashok, C. Pandey
semanticscholar   +1 more source

Analysis of Hetero-Stacked Source TFET and Heterostructure Vertical TFET as Dielectrically Modulated Label-Free Biosensors

IEEE Sensors Journal, 2022
This paper reports an extensive comparison of a hetero-stacked source tunnel field effect transistor (TFET) and heterostructure vertical TFET as label-free biosensors based on dielectric modulation.
K. Vanlalawmpuia, B. Bhowmick
semanticscholar   +1 more source

GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

International journal of numerical modelling, 2023
For the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript.
Kadava R. N. Karthik, C. Pandey
semanticscholar   +1 more source

Optimization of Ferroelectric SELBOX TFET and Ferroelectric SOI TFET

ECS Journal of Solid State Science and Technology, 2020
This paper explores the ferroelectric behavior of silicon doped hafnium oxide incorporated as gate dielectric in Selective Buried Oxide (SELBOX) TFET. In SELBOX TFET a small gap exists in the buried oxide and the electrical parameters are compared with the ferroelectric SOI TFET.
P. Ghosh, B. Bhowmick
openaire   +1 more source

Reduction of Corner Effect in ZG-ES-TFET for Improved Electrical Performance and its Reliability Analysis in the Presence of Traps

ECS Journal of Solid State Science and Technology, 2023
Various electrical parameters of a Z-shaped gate elevated source tunneling field effect transistor (ZG-ES-TFET) in the presence of interface traps are investigated.
Ashok Tammisetti, C. Pandey
semanticscholar   +1 more source

Prospects and Challenges of Different Geometries of TFET Devices for IoT Applications

Nanoscience & Nanotechnology-Asia, 2023
The applications based on IoT are nearly boundless, and the integration of the cyber world and the physical world can be done effortlessly. TFET Based IoT applications may be the future alternative to existing MOSFET-based IoT because of the faster ...
S. K. Sinha, S. Chander, Rekha Chaudhary
semanticscholar   +1 more source

Simulation Study of Dual Metal-Gate Inverted T-Shaped TFET for Label-Free Biosensing

IEEE Sensors Journal, 2022
In this article, an inverted T-shaped tunnel field-effect transistor (TFET) with a dual metal gate (DMG) as a label-free biosensor has been proposed and analyzed using 3-D technology computer aided design (TCAD) simulations.
Yunqi Wang, Cong Li, Ouwen Li, Shan-lin Cheng, Weifeng Liu, Hailong You   +5 more
semanticscholar   +1 more source

Design and Performance Assessment of Dielectrically Modulated Nanotube TFET Biosensor

IEEE Sensors Journal, 2021
The manuscript proposes a novel charge plasma-based junctionless silicon dual cavity nanotube tunnel field-effect transistor (DC-NT-TFET) based biosensor for the detection of neutral and charged biomolecules.
Anju Gedam, B. Acharya, G. P. Mishra
semanticscholar   +1 more source

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

IEEE transactions on nanotechnology, 2021
This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD ...
R. Saha, Yash Hirpara, S. Hoque
semanticscholar   +1 more source

Core-Shell TFET Developments and TFET Limitations

2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2019
Tunneling field-effect transistors (TFET) based on a vertical gate-all-around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current $\mathrm{I}_{\mathrm{o}\mathrm{n}}$ of $6.7\ \mu \mathrm{A}
M. Passlack, P. Ramvall, T. Vasen, A. Afzalian, C. Thelander, K.A. Dick, L.-E. Wernersson, G. Doornbos, M. Holland   +8 more
openaire   +1 more source