Results 171 to 180 of about 118,706,258 (232)
A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor. [PDF]
Micromachines (Basel)Li Z, Gao Z.
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Triggerbare Signalgeneratoren f\"ur einen Pipeline TDC ( Time Digital Converter)
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Design and implementation of a high resolution, multi-hit time-to-digital converter (TDC) on FPGA
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2011 IEEE International Instrumentation and Measurement Technology Conference, 2011
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
semanticscholar +7 more sources
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
semanticscholar +7 more sources
NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
semanticscholar +4 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
semanticscholar +4 more sources
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
semanticscholar +5 more sources
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
semanticscholar +5 more sources
2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
semanticscholar +4 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
semanticscholar +4 more sources
2009 4th IEEE Conference on Industrial Electronics and Applications, 2009
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
null Gao Wu +4 more
semanticscholar +4 more sources
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
null Gao Wu +4 more
semanticscholar +4 more sources
Quantization noise improvement of Time to Digital converter (TDC) for ADPLL
2009 IEEE International Symposium on Circuits and Systems, 2009A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒ c , based on a input reference frequency ...
Jawaharlal Tangudu +8 more
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Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver.
Popong Effendrik +4 more
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