Results 181 to 190 of about 118,706,258 (232)

Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 2020
Time-to-digital converters (TDC) have been widely used in all-digital phase-locked loops (ADPLL). However, the TDC non-linearity and resolution have negatively impacted the ADPLL performance. A better integration between the TDC and ADPLL would improve the performance of the ADPLL, with a minimum increase in power consumption.
Lesley Ferreira, Mateus Moreira, Barbara Souza, Sandro B. Ferreira, Filipe D. Baumgratz, Sergio Bampi   +5 more
openaire   +3 more sources

High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2014
Abstract The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray ...
Weibin Pan, Guanghua Gong, Qiang Du, Hongming Li, Jianmin Li   +4 more
openaire   +2 more sources

A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC), 2013
This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the ...
Weibin Pan, G. Gong, Hong-Ming Li, Jian-Min Li   +3 more
openaire   +2 more sources

A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018
This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator.
Shuya Nakagawa, Kaito Horikoshi, Hiroki Ishikuro   +2 more
openaire   +3 more sources

Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023
Daniel Junehee Lee, Fei Yuan 0005, Yushi Zhou   +2 more
openaire   +3 more sources

A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction

IEEE Transactions on Nuclear Science, 2014
Weibin Pan, G. Gong, Jian-Min Li
semanticscholar   +3 more sources

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2012
C. Hervé, J. Cerrai, T. L. Caër
semanticscholar   +3 more sources

A time-to-digital converter (TDC) with a 13-bit cyclic time domain successive approximation interpolator with sub-ps-level resolution using current DAC and differential switch

Midwest Symposium on Circuits and Systems, 2013
Salim Alahdab, A. Mantyniemi, J. Kostamovaara   +2 more
semanticscholar   +3 more sources

A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS

2021 IEEE 14th International Conference on ASIC (ASICON), 2021
Liu Wang, Guojing Ye, Yumei Huang
openaire   +3 more sources

A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015
A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL).
Yalçin Balcioglu, Günhan Dündar
openaire   +2 more sources