Results 191 to 200 of about 118,706,258 (232)

Design of a high-accuracy time-to-digital converter based on dual-edge signals

Journal of Instrumentation, 2023
Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates.
Yuan Xiao, Huaguo Liang, Li-Wen Jin, Yu-Chuan Wang, Zhi-Wei Shao, Yue Wang, Yingchun Lu   +6 more
semanticscholar   +1 more source

Time-to-digital converter (TDC) based on startable ring oscillators and successive approximation

2014 NORCHIP, 2014
This paper presents a time-to-digital converter (TDC) architecture based on startable ring oscillators (SRO) and the cyclic time domain successive approximation principle. A ring oscillator is first used as a coarse interpolator within the cycle of the reference clock, after which the ring oscillator is used as a phase memory for the time domain ...
Antti Mäntyniemi, Juha Kostamovaara
openaire   +2 more sources

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

IEEE Transactions on Instrumentation and Measurement, 2023
A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multicoarse counters and one fine counter are combined in our TDC architecture.
Xin Yu, Song-Tao Chang, W. Li, Hao-Jie Xia   +3 more
semanticscholar   +1 more source

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation

International Test Conference in Asia, 2023
This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable.
Kentaroh Katoh, Shuhei Yamamoto, Zhe-Ming Zhao, Yu-Jie Zhao, S. Katayama, A. Kuwana, Takayuki Nakatani, K. Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa   +12 more
semanticscholar   +1 more source

A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX field-programmable gate array.

Review of Scientific Instruments, 2022
It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement.
Xin Yu, Hao-Jie Xia, W. Li, Jin Zhang, Song-Tao Chang   +4 more
semanticscholar   +1 more source

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2022
A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage ...
Zhao-Yuan Wang, Yeran Jin, Bo Zhou
semanticscholar   +1 more source

Design and Experiment of Ultrasonic Anemometer Using TDC-GP2 Time-to-Digital Converter

Key Engineering Materials, 2014
An ultrasonic anemometer using TDC-GP2 high-accuracy time measuring chip is studied in this paper, the design of software and hardware parts and principle of flying time measurement using TDC-GP2 chip are also discussed in detail. Under this scheme, a prototype has been fabricated, with simpler circuit architecture.
Han Yu Du, Ming Qin
openaire   +1 more source

7.2 A 48 ×4013.5 mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter

IEEE International Solid-State Circuits Conference, 2021
3D imaging technologies have become prevalent for diverse applications such as user identification, interactive user interfaces with AR/VR devices, and self-driving cars.
Bumjun Kim, Seonghyeok Park, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim   +4 more
semanticscholar   +1 more source

An FPGA-Based Time-to-Digital Converter With Online Dual-Chain Calibration

IEEE Transactions on Instrumentation and Measurement
This article introduces a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with an online dual-chain calibration method to address time resolution and linearity issues arising from the non-uniformity of FPGA internal delay ...
Zheng-Sen Jia, Yu-Zhuo Wang, Jie Ding, Qian Xu, Yadongyang Zhu   +4 more
semanticscholar   +1 more source

A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 μW at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
A two-step time-to-digital converter (TDC) is designed for the high-precision time measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF).
Xinchi Xu, Yonggang Wang, Yonghang Zhou, Zheng-Qi Song, Bo Wu, Xin Lin   +5 more
semanticscholar   +1 more source