Results 201 to 210 of about 118,706,258 (232)
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A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL
IEEE Photonics Conference 2012, 2012We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN +8 more
openaire +1 more source
A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023Daniel Junehee Lee +2 more
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IEEE Transactions on Circuits and Systems - II - Express Briefs
This brief presents a compact gated ring oscillator (GRO) based cyclic time-to-digital converter (TDC) for single-photon emission computed tomography, 3D cameras, and fluorescence lifetime imaging microscopy.
Xin Lu +7 more
semanticscholar +1 more source
This brief presents a compact gated ring oscillator (GRO) based cyclic time-to-digital converter (TDC) for single-photon emission computed tomography, 3D cameras, and fluorescence lifetime imaging microscopy.
Xin Lu +7 more
semanticscholar +1 more source
IEEE transactions on industrial electronics (1982. Print)
This article presents a low-dead-time resolution-adjustable time-to-digital converter (TDC) employing resource-efficient downsampling-multiplexing (DS- MUX) encoding and dual-histogramming based on field-programmable gate array (FPGA).
Shaoxian Liu +3 more
semanticscholar +1 more source
This article presents a low-dead-time resolution-adjustable time-to-digital converter (TDC) employing resource-efficient downsampling-multiplexing (DS- MUX) encoding and dual-histogramming based on field-programmable gate array (FPGA).
Shaoxian Liu +3 more
semanticscholar +1 more source
A Two-Step Time-to-Digital Converter With 5.6-ps Resolution and 1–4255-μs Measurement Range
IEEE Transactions on Circuits and Systems - II - Express BriefsThis brief presents a two-step coarse-fine time-to-digital converter (TDC) for ultrasonic flowmeter applications. To achieve a high resolution with a low frequency reference clock, a 7.7-MHz reference frequency is multiplied by 32 times using a ...
Rong-Zhen Zhu +6 more
semanticscholar +1 more source
A 9-bit Linear Time to Digital Converter Using Pulse Shrinking Rings
National Aerospace and Electronics Conference$\mathrm{A}$ compact linear 9-bit Time to Digital Converter (TDC) has been developed, integrating a pulse shrinking ring consisting of an even number of inverting delay elements with a pulse-arbiter delay line.
Patricia Tutuani +2 more
semanticscholar +1 more source
Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), 2022Rodrigo N. Wuerdig +3 more
openaire +2 more sources
2013
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
openaire +1 more source
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
openaire +1 more source
A Novel Flash-Type Time-To-Digital Converters (TDC) Using GDI Technique
2022Jakka Yeshwanth Reddy +4 more
openaire +1 more source