Results 81 to 90 of about 1,191 (163)

Magnetic-field-to-digital converter using PWM and TDC techniques

, 2006
A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been
Kuo, C.H.; Chen, S.L.; Liu, S.I.
core  

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

Design of a Time-To-Digital Converter with Resolution of Sub-Pico Second

, 2012
計畫編號：NSC100-2221-E032-066 研究期間：20110801~20120731 研究經費：463,000隨著半導體製程之進步，電晶體的操作速度越來越快。相反的，電晶體的操作電壓卻 越來越低，使得以往在電壓域(Voltage Domain)設計電路變得越來越困難。尤其是在 類比數位轉換器的設計上，要達到高解析度變得十分困難。反之，由於電晶體的操作 速度越來越快，因此在時間域(Time domain)上處理訊號可達到的解析度越來越高。因 此運用時間數位轉換器處理訊號可達具有高解析度、省電 ...
施鴻源
core  

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

A Configurable Resolution Time-to-Digital Converter with Low PVT Sensitivity for LiDAR Applications

This paper presents an all-digital and configurable resolution time-to-digital converter (TDC) with low process–voltage–temperature (PVT) sensitivity for light detection and ranging (LiDAR) applications.
Cheng-I Cheng, Hao-Ting Huang, Ruey-Lin Liu, Xiao-Ti Wang, Duo Sheng   +4 more
core   +1 more source

A multichannel and compact time to digital converter for time of flight positron emission tomography [PDF]

, 2015
This paper presents a novel multichannel time to digital converter (TDC) specifically designed for the digitization of photon time of flight (TOF) and energy in positron emission tomography (PET) scanners.
Roberto Roncella, Nahema Marino, DEL GUERRA, ALBERTO, Alberto Del Guerra, MARINO, NAHEMA MAYA KIM GRACE RADOJKA MARITZA M., RONCELLA, ROBERTO, Federico Baronti, Luca Fanucci, Sergio Saponara, SAPONARA, SERGIO, BISOGNI, MARIA GIUSEPPINA, FANUCCI, LUCA, BARONTI, FEDERICO, Maria G. Bisogni   +13 more
core   +1 more source

Application and Comparison of FPGA-Based Carry Chain TDC and DDMTD Schemes in High-Precision Time Synchronization

Sensors
High-precision phase difference measurement based on field-programmable gate arrays (FPGA) has important application requirements in fields such as high-stability time-frequency transmission, signal synchronization, and precision testing.
Yuzhen Huang, Jiajie Yu, Wenlong Xia, Qinggong Guo, Linyu Huang   +4 more
doaj   +1 more source

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

, 2016
This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to
Siek, Liter, Junjie Kong, Doris Schmitt-Landsiedel, Kong, Junjie, Liter Siek, Schmitt-Landsiedel, Doris, Henzler, Stephan, Stephan Henzler   +7 more
core   +1 more source

Low Resource FPGA Based Time-to-Digital Converter

, 2016
For the precise measurement of the time difference between the arrival of different signals coming from the different channels, the time-to-digital converter (TDC) implemented in Field Programmable Gate Array (FPGA) is a very useful device.
Basab B. Purkayastha, Kaustubh Bhattacharyya, Ragib Nasir Ahmed, Sabyasachi Bhattacharyya,
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Design of time-to-digital converter and chip applications

, 2023
Time-to-digital converter (TDC) is very important in products which need precise time meaurement, compact size and low power consumption. In this thesis, a 8-stages GRO (Gated Ring Oscillator) TDC with high resolution and high linearity is presented ...
Xiong, Weihao
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