Results 71 to 80 of about 702 (169)

Design and Validation of a Long-Range Streak-Tube Imaging Lidar System with High Ranging Accuracy

Applied Sciences
The Streak-Tube Imaging Lidar (STIL) has been widely used in high-precision measurement systems due to its ability to capture detailed spatial and temporal information.
Chaowei Dong, Zhaodong Chen, Zhigang Fan, Xing Wang, Lansong Cao, Pengfei Hao, Zhiwei Dong, Rongwei Fan, Deying Chen   +8 more
doaj   +1 more source

2D Vernier žiedinio laikinio skaitmeninio keitiklio modelis / The model of 2D Vernier time to digital converter based on gated ring oscillators

Mokslas: Lietuvos Ateitis, 2018
In this paper, the model of 2D Vernier time to digital converter (TDC) based on gated ring oscillators, which is implemented using VHDL hardware description language, is presented.
Marijan Jurgo, Romualdas Navickas
doaj   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

IEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh   +13 more
doaj   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

IEEE Access
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff   +4 more
doaj   +1 more source

High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA

IEEE Access
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs).
Lorenzo Castelvero, Ignacio H. Lopez Grande, Valerio Pruneri   +2 more
doaj   +1 more source

Time--to--Digital Converter (TDC)--Based Resonant Compute--in--Memory for INT8 CNNs with Layer--Optimized SRAM Mapping

In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more ...
Challagundla, Dhandeep, Bezzam, Ignatius, Islam, Riadul   +2 more
openaire   +2 more sources

Error analysis and correction of high-accuracy modulation domain measurement

Journal of Measurement Science and Instrumentation, 2013
Modulation domain measurement can be u sed to analyze the frequency,phase,and time intervals which transiently change with time.During the implementation of modulation domain analyzer,meas urement errors can be introduced in multiple parts.Aiming at a ...
DU Nian-wen1, ZHU Wei1, MAO Li-ming1
doaj  

An Energy-Efficient LiDAR Receiver Using Time-to-Voltage Converter and SAR ADC in 180 nm CMOS. [PDF]

Micromachines (Basel)
Seo B, Park SM.
europepmc   +1 more source

A 2-GS/s 35.9-fJ/conv.-step Voltage-Time Hybrid Pipelined ADC with Digital Background Calibration in 28-nm CMOS. [PDF]

Micromachines (Basel)
Chang Y, Zhang C, Yang Y, Zhang C, Liu M, Chen D, Yang Y.   +6 more
europepmc   +1 more source