Results 91 to 100 of about 1,191 (163)
Crono TDC : diseño e implementación de un Time to Digital Converter en FPGA.
, 2023 Proyecto Final IntegradorEn este trabajo se presenta el proyecto Crono TDC, el cual consiste en el diseño, implementación y validación de un Time to Digital Converter (TDC) con la capacidad de medir eventos de hasta 5 ns.
Rodríguez, Julián Nicolás
core
, 2013 We present a low-power Time-to-Digital Converter (TDC) chip, fabricated in a standard cost-effective 0.35 μm CMOS technology, which provides 160 ns dynamic range, 10 ps timing resolution and Differential Non-Linearity better than 0.01 LSB rms.
TAMBORINI, DAVIDE +13 more
core +1 more source
Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID
, 2019 © 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology.
Prinzie, Jeffrey +5 more
core +1 more source
Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme
, 2020 This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay ...
Yuan-Ho Chen
core +1 more source
, 2007 本篇論文研究之主要目的，在於時間至數位轉換器(Time-to-Digital Converter, TDC)，又可以稱為時距數位化電路(Time Digitizer)的研製，其主要的功能係量測單擊信號(Single-Shot)波形脈寬或是起始/停止(Start/Stop)信號之間的時距，前述的單擊信號亦可將其上升以及下降邊緣視為起始與停止信號處理，其他相關同一般類比至數位轉換器(Analog-to-Digital Converter, ADC)的定義。近年來由於延遲鎖定迴路(Delay Locked ...
Sung, Chih-Wei, 宋之維
core
An all-digital PLL with a first order noise shaping Time-to-Digital Converter
, 2020 -This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a stateof-art Gated Ring Oscillator (GRO) TDC are described.
Francesco Brandonisio, Franco Maloberti
core
, 2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ...
Liu, Yao-Hong +4 more
core +1 more source
Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS
, 2011 WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access.
Effendrik, P. (author)
core
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
doaj +1 more source
SensorsThis work presents a novel time-to-digital converter based on the analog sampling of dual-phase periodic signals generated from a free-running oscillator.
Roberto Cardella +9 more
doaj +1 more source