Results 91 to 100 of about 118,706,258 (232)

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Journal of Electrical and Computer Engineering, 2011
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase ...
Ni Xu, Woogeun Rhee, Zhihua Wang
doaj   +1 more source

Increasing a resolution of time to digital converter / Laikinio skaitmeninio keitiklio skiriamosios gebos didinimas

Mokslas: Lietuvos Ateitis, 2017
Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS.
Marijan Jurgo, Romualdas Navickas
doaj   +1 more source

Sulfur‐Free Ultrahigh‐Refractive‐Index Polymers Enabled by Densely Packed Oxygen‐Bridged Dibenzofuran‐Cardo Architectures

Advanced Functional Materials, Volume 36, Issue 78, 28 September 2026.
A new class of sulfur‐free, oxygen‐bridged dibenzofuran‐based polymers is developed for ultrahigh‐refractive‐index applications. The rigid π‐extended architecture and enhanced molecular polarizability enable exceptional optical performance, combining refractive indices up to 1.848 with high Abbe numbers and full visible transparency. This work offers a
Hend A. Hegazy, Gyeongsoo Kim, Sooyoung Lee, Mohamed R. Elmasry, Youn‐Chul Kim, Changsik Song   +5 more
wiley   +1 more source

Power-efficient time-to-digital converter for all-digital frequency locked loops

, 2015
An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This ...
Vesterbacka, Mark,, Andersson, Niklas,
core   +1 more source

A Programmable Time Measurement Architecture for Embedded Memory Characterization

, 2005
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time ...
Ross, Neil, Al-Hashimi, Bashir, Collins, Matthew   +2 more
core   +1 more source

Integrated High-Resolution Multi-Channel Time-to-Digital Converters (TDCs) for PET Imaging

, 2011
None
Wu Gao, Deyuan Gao, Christine Hu-Guo, Yann Hu   +3 more
openaire   +3 more sources

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

Electronics
This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO).
Li-Gong Sun, Yixin Luo, Zhi-Feng Deng, Jin-Chan Wang, Bo Liu   +4 more
semanticscholar   +1 more source

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

, 2015
A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.
Ying Wu, Robert Bogdan Staszewski, Wu, Ying, Staszewski, Robert Bogdan, Ping Lu, Lu, Ping, Wu, Ying,, Staszewski, Robert Bogdan,, Lund University., Lu, Ping,   +9 more
core   +2 more sources

An all-digital PLL with a first order noise shaping Time-to-Digital Converter

, 2020
-This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a stateof-art Gated Ring Oscillator (GRO) TDC are described.
Francesco Brandonisio, Franco Maloberti
core  

Design of 8 bit time based analog to digital converter

, 2021
Το αντικείμενο της παρακάτω μεταπτυχιακής εργασίας είναι ο σχεδιασμός και η υλοποίηση ενός Time-Based ADC των 8 bit , ο οποίος χρησιμοποιεί ως Voltage-to-Time Converter (VTC) ένα γραμμικό κυκλώματα μετατροπής ρεύματος σε χρόνο (Linear CTC) και ως Time ...
Νικολόπουλος, Ευστάθιος
core