Results 1 to 10 of about 182 (116)

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment [PDF]

Micromachines, 2023
The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures.
Fuxing Li, Changchun Chai, Yuqian Liu, Yanxing Song, Lei Wang, Yintang Yang   +5 more
doaj   +2 more sources

Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection [PDF]

Nanomaterials, 2022
A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of
Xinyu Zhu, Shurong Dong, Fangjun Yu, Feifan Deng, Kalya Shubhakar, Kin Leong Pey, Jikui Luo   +6 more
doaj   +2 more sources

The ESD Robustness and Protection Technology of P-GaN HEMT [PDF]

Micromachines
This work first analyzes the failure behaviors of P-GaN HEMTs with different gate structures (Schottky gate vs. Ohmic gate) under both forward and reverse ESD stresses.
Yijun Shi, Yantao Chen, Liang He, Xinghuan Chen, Yuan Chen, Guoguang Lu   +5 more
doaj   +2 more sources

Exploration of a Novel Electric-Fuse Device with a Simple Structure of Ni Metal on a SiO₂ Dielectric for Electrostatic Discharge Protection under a Human Body Model [PDF]

Micromachines
On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO2 dielectric for ESD protection was proposed, and ...
He Guan, Jiaying Li, Yangchao Chen, Yongchuan Tang, Yunshuo Li   +4 more
doaj   +2 more sources

Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection [PDF]

Nanoscale Research Letters, 2019
A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing.
Zhuo Wang, Zhao Qi, Longfei Liang, Ming Qiao, Zhaoji Li, Bo Zhang   +5 more
doaj   +2 more sources

Transmission line pulse (TLP) as integrative method for the investigation of ultra-fast trapping mechanisms on high-k MIM [PDF]

Microelectronics Reliability, 2019
This paper discusses the transmission line pulse (TLP) analysis, generally used for electrostatic discharge (ESD) device characterization, as high potential usable tool also for non-ESD structures. TLP technique, combined with DC and pulsed I-V characterization, is performed to study the contribution of trap states on current conduction in metal ...
Merlo, Luca, Rossetto, Isabella, Cerati, Lorenzo, Ghidini, Gabriella, Milani, Antonella, Toia, Fabrizio, Piagge, Rossella, Di Biccari, Leonardo, Gevinti, Eleonora, Croce, Giuseppe, Andreini, Antonio   +10 more
openaire   +4 more sources

Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers [PDF]

Sensors, 2018
High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-μm 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n ...
Shen-Li Chen, Yi-Cih Wu
doaj   +2 more sources

Gate Failure Behavior and Mechanism of AlGaN/GaN HEMTs Under Transmission Line Pulsed Stress

IEEE Journal of the Electron Devices Society, 2021
The failure behavior and the corresponding physical mechanism of the AlGaN/GaN high electron mobility transistors (HEMTs) under transmission line pulse (TLP) stress were investigated in this paper.
Y. Ren, Y. Q. Chen, C. Liu, X. B. Xu, R. Gao, D. Y. Lei, P. Lai, Y. Huang, J. He   +8 more
doaj   +1 more source

Analysis of Trap and Recovery Characteristics Based on Low-Frequency Noise for E-Mode GaN HEMTs Under Electrostatic Discharge Stress

IEEE Journal of the Electron Devices Society, 2021
The ESD effects on the E-mode AlGaN/GaN high-electron mobility transistors (HEMTs) with p-GaN gate are investigated under repetitive TLP pulses. Firstly, the degradation and recovery of output, transfer characteristics, gate-leakage characteristics and ...
X. B. Xu, B. Li, Y. Q. Chen, Z. H. Wu, Z. Y. He, L. Liu, S. Z. He, Y. F. En, Y. Huang   +8 more
doaj   +1 more source

Analyze Scalable Sudoku-Type DTSCR ESD Protection Array Structures in 22nm FDSOI

IEEE Journal of the Electron Devices Society, 2021
This paper reports the design and analysis of scalable Sudoku-type diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharge (ESD) protection structures fabricated in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI ...
Cheng Li, Feilong Zhang, Chenkun Wang, Zijin Pan, Mengfu Di, Albert Wang   +5 more
doaj   +1 more source