Results 11 to 20 of about 5,995,120 (145)
Feasibility study for high bit rate pulse position modulation in fibre communications [PDF]
, 2013 With the rapid progress of optical communication systems, capacity limitation becomes important in high bit rate links. Overcoming this limitation may involve using different modulation and multiplexing methods, including RZ modulation with on-off keying
Ji, Feiyue
core +6 more sources
TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs
Crystals, 2020 For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps.
Zhihua Zhu +5 more
doaj +1 more source
ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation
IEEE Journal of the Electron Devices Society, 2021 Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs.
Mengfu Di +3 more
doaj +1 more source
IEEE Journal of the Electron Devices Society, 2023 The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by
Yi-Chun Huang, Ming-Dou Ker
doaj +1 more source
The simulation of a twelve pulse diode rectifier with saturable reactors [PDF]
, 2004 A twelve pulse diode rectifier with saturable reactors to allow a degree of phase control is simulated using mathematical software. First order differential equations are solved numerically to allow calculation of line current.
Moore, P.J., King, I.G
core +3 more sources
Investigating Graphene gNEMS ESD Switch for Design Optimization
IEEE Journal of the Electron Devices Society, 2021 Traditional in-Silicon PN-junction-based on-chip electrostatic discharge (ESD) protection structures have inherent ESD-induced design overhead problems, including parasitic capacitance, leakage and Si area consumption.
Cheng Li +5 more
doaj +1 more source
Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network
Crystals, 2021 The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network.
Zhihua Zhu +5 more
doaj +1 more source
EMP response modeling of TVS based on the recurrent neural network
Journal of Hebei University of Science and Technology, 2015 Due to the larger workload in the implementation process and the poor consistence between the test results and actual situation problems when using the transmission line pulse (TLP) testing methods, a modeling method based on the recurrent neural network
Zhiqiang JI +3 more
doaj +1 more source
Quantitative TLP Waveform Analysis for GGNmosts
IEEE Journal of the Electron Devices Society, 2018 A method to extract internal physical quantities from transmission line pulse (TLP) waveforms of grounded gate nMOS electro-static discharge protections is presented.
Gijs J. De Raad
doaj +1 more source
A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations
IEEE Journal of the Electron Devices Society, 2018 For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-
Radhakrishnan Sithanandam +1 more
doaj +1 more source