Results 21 to 30 of about 322 (148)

Quantitative TLP Waveform Analysis for GGNmosts

open access: yesIEEE Journal of the Electron Devices Society, 2018
A method to extract internal physical quantities from transmission line pulse (TLP) waveforms of grounded gate nMOS electro-static discharge protections is presented.
Gijs J. De Raad
doaj   +1 more source

InP Low‐Dimensional Nanomaterials for Electronic and Optoelectronic Device Applications: A Review

open access: yesAdvanced Sensor Research, Volume 2, Issue 10, October, 2023., 2023
Due to their suitable direct bandgap, high carrier mobility, and size‐dependent physical properties, low‐dimensional InP nanostructures have attracted great attention from scientists. In this Review, recent advances in low‐dimensional InP materials including synthetic methods, physical properties, and applications in electronics and optoelectronics are
Lin‐Qing Yue   +6 more
wiley   +1 more source

A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations

open access: yesIEEE Journal of the Electron Devices Society, 2018
For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-
Radhakrishnan Sithanandam   +1 more
doaj   +1 more source

Highly Efficient Van Der Waals Heterojunction on Graphdiyne toward the High‐Performance Photodetector

open access: yesAdvanced Science, Volume 10, Issue 25, September 5, 2023., 2023
Here, for the first time, a highly effective graphdiyne/molybdenum (GDY/MoS2) type‐II heterojunction in a charge separation is reported toward a high‐performance photodetector. The device exhibits broadband detection (453–1064 nm) with a maximum responsivity of 78.5 A W−1 and a high speed of 50 µs.
Dinh Phuc Do   +14 more
wiley   +1 more source

Transmission line pulse based reliability investigations of HBTs [PDF]

open access: yes, 1997
We propose transmission line pulse (TLP) stress instead of DC bias stress in order to stimulate different failure mechanisms for HBTs for wafer level reliability characterisation and show the effects of degradation on the device performance.
Brandt, M.   +7 more
core   +1 more source

Transmission line pulse stress on thick film resistors

open access: yes, 2022
S.70-75One of the most important issues of resistors properties is the value stability under different electrical and non electrical influences. Mechanical and/or thermal stress together with the electrical one represents the main factors that have a ...
Gieser, H.   +5 more
core   +1 more source

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

open access: yesIEEE Access, 2020
As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications.
Yang Wang   +5 more
doaj   +1 more source

Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method

open access: yes, 2000
International audienceFor many years,design of robust ESD cell becomes critical due to the ever increasing density of technology process. This paper presents the main results of a numerical investigation of a Grounded Gate NMOS Transistor (GGNMOST) under
Galy, P.   +7 more
core   +4 more sources

An Improved Experimental Setup For Electrostatic Discharge (Esd) Measurements Based On Transmission Line Pulsing Technique

open access: yes, 2001
Transmission line pulsing (TLP) is a useful technique to characterize electrostatic discharge (ESD) events in semiconductor devices. The pulse waveforms generated by a typical TLP setup, however, are often distorted and oscillatory.
Young, R., Lee, Jui Chu, Liou, Juin J.
core   +2 more sources

Deep sub-micron ESD GGNMOS layout design and optimization

open access: yesMATEC Web of Conferences, 2018
In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design.
Jun Shi
doaj   +1 more source

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