High current characteristics of copper interconnect under transmission-line pulse (TLP) stress and ESD zapping
An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs
Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement
Electrostatic test structures for transmission line pulse and human body model testing at wafer level
TLP calibration, correlation, standards, and new techniques [ESD test]
