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, 2021 International audienceUsing TLP (Transmission Line Pulse) and VF-TLP (Very Fast Transmission Line Pulse) to emulate a fast transient stress, a study of oxide reliability during a CDM (Charged Devise Model) event was done to establish an empirical law ...
Emmanuel Simeu, Jean-Daniel Arnould
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Fine Modeling of Transmission Line Pulse (TLP) and Exploitation for Measurement Set-Up Optimization
9th International Symposium on EMC Joint with 20th International Wroclaw Symposium on EMC, EMC Europe 2010, 2010Lafon, F. +5 more
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Transient analysis of latent damage formation in SMD capacitors by Transmission Line Pulsing (TLP)
Microelectronics Reliability, 2017Abstract Latent defects were provoked in SMD capacitors by short TLP current pulses. Simultaneously the transient evolution of the device's charge was extracted to generate its Q(V) characteristics and to determine its capacitive behaviour during the transient current stress.
Dennis Helmut +2 more
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Microelectronics Reliability, 2011
Abstract We present a new method for the on-wafer-characterisation for the reverse recovery behaviour of integrated diodes, which can perform on-wafer automated measurements over a wide range of different bias and pulsing conditions. The system is based on a Transmission-Line-Pulsing (TLP) technique and can be used to characterise diodes down to the
Martin Sauter +3 more
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Abstract We present a new method for the on-wafer-characterisation for the reverse recovery behaviour of integrated diodes, which can perform on-wafer automated measurements over a wide range of different bias and pulsing conditions. The system is based on a Transmission-Line-Pulsing (TLP) technique and can be used to characterise diodes down to the
Martin Sauter +3 more
openaire +1 more source
Microelectronics Reliability, 2005
This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests.
Heinrich Wolf +3 more
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This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests.
Heinrich Wolf +3 more
openaire +1 more source
Microelectronics Reliability, 2003
Abstract Electrostatic discharge events can degrade the electromigration (EM) reliability of devices. Transmission line pulsing stress analysis is used to evaluate electrostatic discharge robustness of copper (Cu) interconnects and the impact to EM performance.
Sherry Suat Cheng Khoo +2 more
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Abstract Electrostatic discharge events can degrade the electromigration (EM) reliability of devices. Transmission line pulsing stress analysis is used to evaluate electrostatic discharge robustness of copper (Cu) interconnects and the impact to EM performance.
Sherry Suat Cheng Khoo +2 more
openaire +1 more source
IEEE Electron Device Letters, 2008
Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a DC curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing (TLP)-measured holding voltage.
Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang
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Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a DC curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing (TLP)-measured holding voltage.
Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang
openaire +1 more source
2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004
ESD robustness of Low Temperature Poly-Si (LTPS) diodes and TFT devices has been investigated in this paper. By using the Transmission Line Pulsing (TLP) techniques, the It2 (secondary breakdown current) of LTPS diodes and TFT devices were measured. To evaluate the ESD robustness of components for ESD protection, the shifts of breakdown voltage and cut-
null Ming-Dou Ker +4 more
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ESD robustness of Low Temperature Poly-Si (LTPS) diodes and TFT devices has been investigated in this paper. By using the Transmission Line Pulsing (TLP) techniques, the It2 (secondary breakdown current) of LTPS diodes and TFT devices were measured. To evaluate the ESD robustness of components for ESD protection, the shifts of breakdown voltage and cut-
null Ming-Dou Ker +4 more
openaire +1 more source
2004 IEEE International Reliability Physics Symposium. Proceedings, 2004
The Cu metal interconnect under TLP stress can not be treated as the constant current stress. The increase in the metal interconnect length at GGNMOS drain can improve device's MM failure threshold but degrade device's HBM failure threshold and IT2.
J.H. Lee +7 more
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The Cu metal interconnect under TLP stress can not be treated as the constant current stress. The increase in the metal interconnect length at GGNMOS drain can improve device's MM failure threshold but degrade device's HBM failure threshold and IT2.
J.H. Lee +7 more
openaire +1 more source