Results 1 to 10 of about 8,987 (189)
Electrical and Mechanical Analysis of Different TSV Geometries
Metals, 2020 Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing.
Alireza Eslami Majd +2 more
exaly +3 more sources
Low Stress TSV Arrays for High-Density Interconnection
EngineeringIn three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W–
Xueyong Wei +2 more
exaly +3 more sources
Modeling and analyzing coupling noise effect of Cu-carbon nanotube composite through-silicon vias interconnects using NILT based [PDF]
Serbian Journal of Electrical Engineering, 2023 In the modern field of microelectronics, the performance of interconnects tends to decrease as the technology node advances. Therefore, Cu-CNT composite TSV interconnects are utilized due to their favorable performance.
Ait Belaid Khaoula +3 more
doaj +1 more source
Humidity in the walls from aerated concrete for conditions northeast Asia [PDF]
E3S Web of Conferences, 2023 The influence of the characteristics of external finishing coatings on the humidity regime in walls made of aerated concrete grades D350-D500 for buildings located in the geographic subregion of Northeast Asia has been assessed.
Loganina Valentina +2 more
doaj +1 more source
Thermal Comfort and Energy Efficiency on Air-Conditioned University Classrooms by means of CFD-Simulation [PDF]
E3S Web of Conferences, 2023 This paper proposed a method to forecast thermal comfort conditions and energy efficiently in air-conditioned classrooms. Room comfort parameters such as temperature and wind speed are simulated using the computational fluid dynamics (CFD) tool.
Pham Hong-Tham T. +3 more
doaj +1 more source
Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC [PDF]
2011 12th International Symposium on Quality Electronic Design, 2016 TSV in 3DIC introduces a large and fickle parasitic capacitance inevitably, causing serious problems on Power/Signal Integrity (P/SI). In this paper, we give two methods to mitigate TSV-to-TSV coupling, which are buffer insertion and shield insertion. The effect of the buffer insertion and shield insertion are studied by comparison experiment, and the ...
Quan Deng 0003 +3 more
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Dianzi Jishu Yingyong, 2021 This paper reviews the reliability of TSV(through silicon via) in three aspects: thermal stress, process and piezoresistive effect. The thermal stress reliability of TSV is reflected in the great difference of thermal expansion coefficient between ...
Wang Shuo, Ma Kui, Yang Fashun
doaj +1 more source
Establishment of quantitative nested-PCR of Abelson interactor 1 transcript variant-11
Heliyon, 2022 Abelson interactor 1 (ABI1), which presents 18 Transcript Variants (TSV), plays an important role in CRC metastasis. Different ABI1-TSVs play synergistic or antagonistic roles in the same pathophysiological events. ABI1 Transcript Variant-11 (ABI1-TSV-11)
Tingru Lin +5 more
doaj +1 more source
Engineering Reports, 2022 Through‐silicon via (TSV) technology is a key technology to realize multi‐layer chips and its structure model and transmission characteristics have attracted much attention.
Wenbo Guan +3 more
doaj +1 more source
Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications
Memories - Materials, Devices, Circuits and Systems, 2023 The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV ...
Tzu-Heng Hung +2 more
doaj +1 more source