Results 211 to 220 of about 606,110 (277)

Performance Assessment of New Dual-Pocket Vertical Heterostructure Tunnel FET-Based Biosensor Considering Steric Hindrance Issue

IEEE Transactions on Electron Devices, 2019
In this paper, a new dual-pocket (DP), dielectric modulated (DM) heterostructured tunnel field-effect transistor (DM-HTFET)-based biosensor has been reported.
Amit Bhattacharyya, M. Chanda, D. De
semanticscholar   +1 more source

Tunneling FET Fabrication and Characterization

2016
Since the early demonstration of the conventional p + −i − n + Tunneling FETs (TFETs), various tunneling junction designs as well as the introduction of new material systems enabled the performance of TFETs to improve by orders of magnitude. Different properties and considerations of the material systems require well designed processes and novel ...
Tao Yu, Judy L. Hoyt, Dimitri A. Antoniadis   +2 more
openaire   +1 more source

InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs

2012 International Electron Devices Meeting, 2012
In this paper we present vertical tunnel diodes and tunnel FETs (TFETs) based on III-V-Si nanowire heterojunctions. We experimentally demonstrate InAs-Si Esaki tunnel diodes with record high currents of 6 MA/cm2 at 0.5 V in reverse bias. Furthermore, we have fabricated vertical InAs-Si nanowire TFETs with gate-all-around architecture and high-k ...
H. Riel, K. E. Moselund, C. Bessire, M. T. Bjork, A. Schenk, H. Ghoneim, H. Schmid   +6 more
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Steep Slope Tunnel FET Simulation

2017
The simplest way for increasing the transistor density in the wafer is to reduce the feature size of transistor.
Yung-Chun Wu, Yi-Ruei Jhan
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Simulation study of nanowire tunnel FETs

70th Device Research Conference, 2012
Tunnel FETs (TFETs) are candidates for low-power logic switches with sub-thermal slope which could enable a strongly reduced supply voltage. To improve the ON-current compared to Si TFETs, III–V/Si hetero junctions have been proposed [1]. Using nanowires has additional advantages: (i) the possibility of many different material combinations [2], (ii ...
Andreas Schenk, Reto Rhyner, Mathieu Luisier, Cedric Bessire   +3 more
openaire   +1 more source

Tunnel FETs for low power electronics

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016
We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than ...
Anne Vandooren, Alireza Alian, Anne Verhulst, Jacopo Franco, Rita Rooyackers, Quentin Smets, Devin Verreck, Niamh Waldron, Dan Mocuta, Nadine Collaert   +9 more
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Assessment of Hetero-Structure Junction-Less Tunnel FET’s Efficacy for Biosensing Applications

Sensing and Imaging, 2023
Rabiya Abdulnassir, Avtar Singh, Dereje Tekilu, Gangiregula Subarao, M. Chanda   +4 more
semanticscholar   +1 more source

Gate-Induced Source Tunneling FET (GISTFET)

IEEE Transactions on Electron Devices, 2015
We propose a device, the gate-induced source tunneling FET (GISTFET), that uses two gate work functions to modulate lateral tunneling. The performance of the device is largely independent of the details of the chemical doping profile, potentially freeing device design from issues related to solid solubility, junction abruptness, and dopant variability.
Andrew Pan, Chi On Chui
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Temperature Dependence of Analog Performance, Linearity, and Harmonic Distortion for a Ge-Source Tunnel FET

IEEE Transactions on Electron Devices, 2020
In this article, we report an investigation of the effects of variation in temperature in the range of 300–450 K on the analog performance and harmonic distortion (HD) characteristics of a Ge-source tunnel FET (TFET) using a numerical device simulator ...
Emona Datta, A. Chattopadhyay, A. Mallik, Y. Omura   +3 more
semanticscholar   +1 more source

Multi-Gate Tunneling FETs

2009
In Chap. 5 the integration of tunneling FETs in a low-power multi-gate technology is discussed as example for an alternative device concept and as outlook to analog design aspects beyond CMOS. Analog design considerations are derived from basic device performance, temperature and matching behavior.
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