Results 221 to 230 of about 606,110 (277)
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Short-Channel Effects in Tunnel FETs
IEEE Transactions on Electron Devices, 2015This paper investigates short-channel effects (SCEs) in double-gate tunnel FETs (TFETs) using an analytic model that includes depletion in the source. It is shown that the drain bias has a significant effect on the potential profile at the source when the channel length is reduced to below twice the scale length.
Jianzhi Wu, Jie Min, Yuan Taur
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Complementary III–V heterostructure tunnel FETs
2016 46th European Solid-State Device Research Conference (ESSDERC), 2016In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with I on of a couple of µA/µm
K. E. Moselund +5 more
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A Novel Barrier Controlled Tunnel FET
IEEE Electron Device Letters, 2014A novel structure of tunnel field-effect transistor (FET) is introduced with the gate composed of three segments of different work functions. The tunnel current is controlled by an in channel potential barrier as well as the source-channel tunnel junction bandgap, which combines the merits of both bandgap-controlled tunnel FET and barrier-controlled ...
Wang, Hao +7 more
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Tunnel FET technology: A reliability perspective
Microelectronics Reliability, 2014Abstract Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage ( V DD ) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS).
Suman Datta +2 more
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ESD Behavior of Tunnel FET Devices
IEEE Transactions on Electron Devices, 2017For the first time, we present the electrostatic discharge (ESD) behavior of grounded gate tunnel FET (ggTFET) with detailed physical insight into the device operation, 3-D filamentation and failure under ESD stress conditions. Current as well as time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the unique failure ...
Nagothu Karmel Kranthi +1 more
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Performance analysis of heterojunction tunnel FET device with variable Temperature
Applied Physics A, 2021I. A. Pindoo, S. K. Sinha, S. Chander
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VLS-grown silicon nanowire tunnel FET
2009 Device Research Conference, 2009In the present work we demonstrate the successful implementation of tunneling field-effect transistors (TFETs) based on silicon nanowires (Si NWs) that were grown using the vapor-liquid-solid (VLS) growth method. Device optimization resulted in increased band-to-band tunneling with an on-current of 0.5mA/mm, and I on /I off ratio of about 6 decades ...
K. E. Moselund +7 more
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Resonant tunneling through interface traps in nanowire tunneling FET
2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013), 2013The tunneling field-effect-transistor (TFET) is very promising for low power CMOS devices due to a steep subthreshold slope typically lower than 60mV/dec. One of the major issues with this structure is the surface states at the gate dielectric interface. In this study a nanowire TFET with InAs-GaSb heterojunction is numerically simulated to examine the
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