Results 191 to 200 of about 8,846,054 (209)

Innovative V-NAND Flash Structure with Dual Trap Layer for Future Generations of Multi-Bit Device

2025 IEEE International Memory Workshop (IMW)
The primary strategy for high-capacity storage NAND flash memory is to increase the number of bits per cell without process-related hardship. The novel vertical NAND (V-NAND) flash structure with a back gate and a pair of trap (Dual Trap) layers facing a
Jeongyoon Yeo, Joonsung Kim, Younghwan Son, Taein Lee, Sejun Park, Min-Kyu Jeong, Jung Hoon Lee, Suk-Kang Sung, Dongku Kang, Seungwan Hong, Sung Hoi Hur   +10 more
openaire   +2 more sources

First Demonstration of Threshold Voltage Modeling in Multi-Hole V-NAND Flash Architecture with Noncircular Channel Hole Profiles

2025 IEEE International Memory Workshop (IMW)
A predictive 3D parasitic capacitance modeling for multi-hole 3D vertical NAND (V-NAND) is first suggested to reflect geometric variations in mold height, dielectric thickness, critical dimension, hole pitch, and hole-to-cut variation due to the wordline
Chanyang Park, Min-Kyu Jeong, Taein Lee, Sejun Park, Jung Hoon Lee, Yujin Lee, Seungwan Hong, Sung Hoi Hur   +7 more
openaire   +2 more sources

Highly Scalable Vertical Bypass RRAM Using Interface-Type Resistive Switching Mechanism for V-Nand memory Applications

IEEE Transactions on Electron Devices
In this study, we present a vertical bypass resistive random access memory (VB-RRAM) that integrates interface-type resistive switching RRAM with excellent memory characteristics for V-NAND applications.
Geonhui Han, Jongseon Seo, Kyumin Lee, Dongmin Kim, Yoori Seo, Jinwoo Lee, Jinmyung Choi, Dongho Ahn, Sechung Oh, Hyunsang Hwang   +9 more
openaire   +2 more sources

Bypass Resistive RAM With Interface Switching-Based Resistive RAM and InGaZnO Bypass Transistor for V-NAND Applications

IEEE Electron Device Letters
We report a bypass resistive random-access memory (B-RRAM), which combines interface switching-based RRAM and an IGZO transistor, providing high compatibility with a vertical NAND (V-NAND) structure for high-density memory.
Geonhui Han, Kyumin Lee, Dongmin Kim, Yoori Seo, Jinwoo Lee, Jinmyung Choi, Dongho Ahn, Sechung Oh, Hyunsang Hwang   +8 more
openaire   +2 more sources

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance.
Jae-Woo Im, Woo-Pyo Jeong, Doo-Hyun Kim, Sang-Wan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, You-Se Kim, Hyun-Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jin-Ho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doo-Sub Lee, Ji-Ho Cho, Oh-Suk Kwon, Ji-Sang Lee, Moo-Sung Kim, Sang-Hyun Joo, Jae-Hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kye-Hyun Kyung, Jeong-Hyuk Choi   +33 more
openaire   +2 more sources

High Performance HfLaO-based TiO₂-Channel FE V-NAND with High Consistency and Low Operation Voltage

2024 IEEE Silicon Nanoelectronics Workshop (SNW)
A novel 3D vertical NAND (V-NAND) ferroelectric field-effect transistor (FeFET) array with TiO2 channel and HfLaO ferroelectric layer has been demonstrated. The fabricated FeFETs exhibit excellent performances, including high device-to-device consistency
Xujin Song, Shangze Li, Dijiang Sun, Xiaoyan Liu, Jinfeng Kang   +4 more
openaire   +2 more sources

Suppression of Self-Heating Effects in 3-D V-NAND Flash Memory Using a Plugged Pillar-Shaped Heat Sink

IEEE Electron Device Letters, 2019
Self-heating effects (SHEs) in 3-D V-NAND flash memory are investigated using simulations. First, temperature increase is estimated during the read operation, and a hot spot region along the bit-line is identified. Then, a novel bilayered macaroni filler is proposed to relieve the SHEs.
Jun-Young Park, Dae-Hwan Yun, Seong-Yeon Kim, Yang-Kyu Choi   +3 more
openaire   +2 more sources

Improvement of Thermal Stability in Dual Mechanism Memory Using Hf_xAl_1-xO Blocking Layer for 3D V-NAND Flash Application

IEEE Electron Device Letters
Dual mechanism memory, which combines charge trapping and polarization switching, was demonstrated as a way to overcome the limited memory window of charge trap flash (CTF) memory. However, due to the poor thermal stability of the Hfy Zr $_{\text {1-y}}$
Jun Hong Chu, Sheung Hun Kim, Changyeon Kang, Eui Joong Shin, Jaejoong Jeong, Youngkeun Park, Byung Jin Cho   +6 more
openaire   +2 more sources

V-Ramp V_BD Prediction Method Using OCD-Spectrum and Deep-Learning, and Application to Early Detection of V-NAND Low Metal Reliability Risk

2024 IEEE International Reliability Physics Symposium (IRPS)
For the first time, we propose a method to predict V-ramp VBD(Breakdown Voltage) using deep learning from OCD (Optical Critical Dimension)-spectrum. Using this, it was shown that the inter-metal dielectric VBD occurring in the LM (low metal) layers of V ...
Sungman Rhee, Sung-Pyo Park, Sangku Park, Yuchul Hwang, Sangwoo Pae, Jun Meng, Yoonju Park   +6 more
openaire   +2 more sources

Analysis of Program Characteristics in V-NAND with Varying Dimple Length

Journal of the Institute of Electronics and Information Engineers
Seongwoo Kim, Myounggon Kang
openaire   +2 more sources