Results 251 to 260 of about 36,083 (304)

Design of a vector processor

Journal of Computer Science and Technology, 1986
This paper discusses the inherent parallelism limits on several applications for vector computers, the parallel capabilities of several architectures and two ways (traditional instruction control flow and data control flow) by which the capabilities can be used. Then a scheme for a pipelined vector processor of multi-processing units is presented.
exaly   +2 more sources

The abstract vector processor

Microprocessors and Microsystems, 2006
Abstract The abstract vector processing unit (VPU) is a virtual VPU that represents a set of real VPUs. It has an idealised instruction set and constraints common to the VPUs that it represents. Together, the idealised instruction set and common constraints allow programs to be portable and to perform efficiently on the real VPUs being represented ...
Lai, Bing-Chang, McKerrow, Phillip J, Abrantes, Maria   +2 more
openaire   +2 more sources

Arithmetic for vector processors

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH), 1987
In electronic computers the elementary-arithmetic operations are these days generally approximated by floating-point operations of highest accuracy. Vector processors and parallel computers often provide additional operations like “multiply and add”, “accumulate” or “multiply and accumulate”.
Reinhard Kirchner, Ulrich W. Kulisch
openaire   +1 more source

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology [PDF]

, 2022
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC.
Mendoza Escobar, Jonnatan, Cabo Pitarch, Guillem, Kostalampros, Ioannis-Vatistas, López Paradís, Guillem, Montabes, Víctor, Hernández Luz, Carles, Ruíz Ramírez, Abraham Josafat, Langarita Benítez, Rubén, Jiménez Arador, Víctor, Minervini Minervini, Francesco, Valero Cortés, Mateo, Pavón Rivera, Julián, Rubio Sola, Jose Antonio, González Trejo, Alberto, Dominguez de la Rocha, Marc, Ramírez Lazo, Cristóbal, Marimon Illana, Joan, Cristal Kestelman, Adrián, Candon, Gerard, Vargas Valdivieso, Iván, Carril, Xavier, Leyva Santes, Neiel Israel, Palomar Pérez, Óscar, Rojas Morales, Carlos, Hernández Calderón, César Alejandro, Moretó Planas, Miquel, Fontova, Pau, Sonmez, Nehir, Doblas Font, Max, Soria Pardos, Víctor, Moll Echeto, Francisco de Borja, Unsal, Osman Sabri, Reggiani, Enrico, Rodas, Narcis, Figueras Bagué, Roger, Rodriguez, Mario   +35 more
exaly   +2 more sources

Logic simulation on vector processors

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers, 2003
The performance of three commercial vector computers, the Cray X-MP/48, IBM 3090/400, and Alliant FX/8, for simulating logic circuits at gate level is compared. Experiments that assume zero- and unit-delay models demonstrate that certain key architectural features, especially, the presence of a scalar cache, have an adverse impact on the potential ...
Ram Raghavan, John P. Hayes, William R. Martin   +2 more
openaire   +1 more source

The effectiveness of caches for vector processors

Proceedings of the 8th international conference on Supercomputing - ICS '94, 1994
Vector processors have typically used vector registers, interleaved memory, and pipelined access to data to provide sufficient memory system performance. Caches have been used mainly for instructions and scalar data, while vectors are usually uncached, presumably partially because of the belief that there is insufficient vector locality in these ...
Jeffrey D. Gee, Alan Jay Smith
openaire   +1 more source

Vectorized transforms in scalar processors

IEEE Signal Processing Magazine, 2002
We disclose a generalized approach to creating efficient implementations of linear, orthogonal transforms, with specific examples discussed for the 8 x 8 DCT used in image compression. We connect this with a method for performing signed, parallel processing in scalar, off-the-shelf processors for integer transforms.
Jennifer Q. Trelewicz, Joan L. Mitchell, Michael T. Brady   +2 more
openaire   +1 more source

OPSILA: a vector and parallel processor

IEEE Transactions on Computers, 1993
A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes.
Fernand Boéri, Michel Auguin
openaire   +1 more source

An APL Compiler for a Vector Processor

ACM Transactions on Programming Languages and Systems, 1984
Summary: Although vector processors have been available for over a decade, the software necessary to make effective use of these facilities has generally not been available. In this paper the design of a compiler for the programming language APL, which produces code that allows most operations to be performed in parallel, is described.
openaire   +2 more sources

Accurate arithmetic for vector processors

Journal of Parallel and Distributed Computing, 1988
Abstract In addition to the four elementary arithmetic operations, more advanced electronic computers such as vector and parallel computers often provide a number of compound operations as additional elementary operations. If pipelined compound operations like “multiply and add,” “accumulate,” and “multiply and accumulate” contribute essentially to ...
Reinhard Kirchner, Ulrich W. Kulisch
openaire   +1 more source