Results 271 to 280 of about 36,083 (304)

Scalable vector processors for embedded systems

IEEE Micro, 2003
For embedded applications with data-level parallelism, a vector processor offers high performance at low power consumption and low design complexity. Unlike superscalar and VLIW designs, a vector processor is scalable and can optimally match specific application requirements.To demonstrate that vector architectures meet the requirements of embedded ...
Christoforos E. Kozyrakis, David A. Patterson 0001   +1 more
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Scheduling Vector Straight Line Code on Vector Processors

1992
We present an algorithm to schedule basic blocks of vector three-address-instructions. This algorithm is suited for a special class of vector processors containing a buffer (register file) which may be partitioned arbitrarily into vector registers by the user. The algorithm computes the best ratio of vector register spilling to strip mining, taking the
Christoph W. Keßler, Wolfgang J. Paul, Thomas Rauber   +2 more
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FFT on a new parallel vector processor

1986
A new parallel processing system has been proposed, and a prototype model of the system has been constructed. It is designed to perform parallel vector operations at maximum efficiency. In addition, it can also handle communicating vector operations, and hence exploit irregular parallelism present in many apparently sequential algorithms. The system is
Kung-Kiu Lau, Xiang-Zhen Qiao
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A multithreaded vector co-processor

1997
A multithreaded vector co-processor design is described. It is intended to be placed with its private vector memory, on an expansion board, linked to the scalar processor and its cache-based memory hierarchy. The vector co-processor can run up to 8 vector tasks (threads) in parallel. Vector registers can be accessed either as independent sets of scalar
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The power of a one-dimensional vector of processors

1981
Kung [1979b] has recently enunciated a set of principles for designing algorithms for implementation in Very Large Scale Integrated circuitry (VLSI), and supported these principles by displaying a number of particular algorithms based on various "communication geometries". In this paper we will examine a communication geometry which Kung calls the "one-
Jon Louis Bentley, Thomas Ottmann
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THE USE OF VECTOR PROCESSORS IN RESERVOIR SIMULATION

Proceedings of SPE Reservoir Simulation Symposium, 1979
Abstract Tests of reservoir simulation models on the IBM 3838 array processor and CRAY-1 computer are described. The tests involved the use of a benchmark-type reservoir simulation model with a fixed set of data.
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Memory access reordering in vector processors

Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture, 2002
Interference among multiple vector streams that access memory concurrently is the major source of performance degradation in main memory of pipelined vector processors. While totally eliminating interference appears to be impossible, little is known on how to design a memory system that can reduce it. In this paper, we introduce a concept called memory
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An ISA Comparison Between Superscalar and Vector Processors

1999
Q1
Francisca Quintana, Roger Espasa, Mateo Valero   +2 more
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Vector Processors

2023
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An intermediate language for vector processors

Proceedings of the 28th annual Southeast regional conference on - ACM-SE 28, 1990
Abbas S. Youssefi, D. E. Stevenson
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