Results 261 to 270 of about 36,083 (304)

SX-ACE processor: NEC's brand-new vector processor

2014 IEEE Hot Chips 26 Symposium (HCS), 2014
exaly   +2 more sources

Vector processor customization for FFT

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2011
Processors and memory systems suffer from a growing performance gap between them. Each technology generation increases the on-chip performance capabilities however, memory bandwidth increases at a much slower pace. Therefore, overall performance improvements are constrained by the available memory bandwidth.
Bogdan Spinean, Georgi Kuzmanov, Georgi Gaydadjiev   +2 more
openaire   +1 more source

Modeling mutation and a vector processor

Proceedings. [1989] 11th International Conference on Software Engineering, 2003
Mutation analysis is a software testing methodology designed to substantiate the correctness of a program Phi . The mutation approach is to induce syntactically correct changes in Phi , thereby creating a set of mutant programs. The goal of a tester is to construct a set of test data T that distinguishes the output of Phi (T) from that of all mutant ...
Aditya P. Mathur, Edward W. Krauser
openaire   +2 more sources

Vectorization of robot dynamics on a pipelined vector processor

Proceedings. 1991 IEEE International Conference on Robotics and Automation, 2002
A computational scheme for a pipelined vector processor for robot inverse dynamics is presented. Vectorization of the inverse dynamics computation is achieved while the dynamics formulation still remains within the general linear recursive framework, which is based on Newton-Euler equations and originally designed for scalar processing.
Harry H. Cheng, Krishna C. Gupta
openaire   +1 more source

A Deep Learning Compiler for Vector Processor

2021
The technical route of machine learning compiler generally refers to the application of automatic or semi-automatic code generation in the optimization process instead of hand-optimization. This paper presents a deep learning compiler (DLCS) for target vector processor based on LLVM framework, which lowers deep learning (DL) models to an intermediate ...
Pingping Pan, Jun Wu 0006, Songyuan Zhao, Haoqi Ren, Zhifeng Zhang 0001   +4 more
openaire   +1 more source

Vectorization of robot inverse dynamics on a pipelined vector processor

IEEE Transactions on Robotics and Automation, 1993
This paper presents a computational scheme on a pipelined vector processor for robot inverse dynamics. Vectorization of the inverse dynamics computation is achieved while the dynamics formulation still remains within the general linear recursive framework. Parametric studies are conducted on a commercially available pipelined vector processor. The 1.82
Harry H. Cheng, Krishna C. Gupta
openaire   +1 more source

Bisection is not Optimal on Vector Processors

SIAM Journal on Scientific and Statistical Computing, 1989
The bisection method for computing eigenvalues of symmetric tridiagonal matrices and its natural extension - the multisection method - are compared. A simple analysis and some numerical examples show that the bisection method is in general not optimal in the class of multisection methods for the extraction of one eigenvalue on vector processors.
openaire   +1 more source

An on-chip cache design for vector processors

Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, 2007
This paper discusses the potential of an on-chip cache memory for modern vector supercomputers. The vector supercomputers can achieve the high computational efficiency for compute-intensive scientific applications. The most important factor affecting the computational performance is high memory bandwidth to provide a sufficient amount of data to the ...
Akihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi   +5 more
openaire   +1 more source

Adding a vector unit to a superscalar processor

Proceedings of the 13th international conference on Supercomputing, 1999
1
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero   +3 more
openaire   +2 more sources

The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture

Programming and Computer Software, 2017
The complexity of software is ever increasing, and it requires more and more computational resources for its execution. A way to satisfy these requirements is the use of vector instructions that can operate with fixed-length vectors of data of the same.
openaire   +1 more source