IFA-ICP: A Low-Complexity and Image Feature-Assisted Iterative Closest Point (ICP) Scheme for Odometry Estimation in SLAM, and Its FPGA-Based Hardware Accelerator Design. [PDF]
Sensors (Basel)Li JE, Hwang YT.
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Single-shot matrix-matrix photonic processor based on spatial-spectral hypermultiplexed parallel diffraction. [PDF]
Nat CommunLuan C +4 more
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Image-Based Volatile Organic Compound Identification Using the Cosine Similarity Method. [PDF]
ACS OmegaMao J, Wu Z, McLoone S, Shakeel H.
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Studies on Main Memory Database Systems for Vector Processors
Studies on Main Memory Database Systems for Vector Processorsopenaire
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A Minimal RISC-V Vector Processor for Embedded Systems
2020 Forum for Specification and Design Languages (FDL), 2020This paper presents the first RISC-V vector processor design aimed at microcontrollers that uses the new RISC-V ‘V’ extension for vectors, part of the open-source RISC-V instruction set architecture (ISA). Being aimed at small embedded devices, it demonstrates a simpler method of parallel execution than traditional vector architectures to minimise ...
Tom J Kazmierski
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On the effective bandwidth of interleaved memories in vector processor systems
IEEE Transactions on Computers, 1985Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth.
Wilfried Oed, Otto Lange
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The architecture of a multi-vector processor system, VPP
Parallel Computing, 1988Abstract The VPP system is a multi-vector processor system which mainly aims at effective satellite image processing. It consists of up to 64 element processors (PUs), an S-D loop network, and an image memory. The PUs can execute flexible vector processing by a new vector access method, ‘Index-set’.
Atsushi Inoue, Akira Maeda
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Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems
IEEE Embedded Systems Letters, 2023Dejian Li, Meng Liu
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DVINO: A RISC-V Vector Processor Implemented in 65nm Technology [PDF]
, 2022 This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC.
Mendoza Escobar, Jonnatan +35 more
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Scalable vector processors for embedded systems
IEEE Micro, 2003For embedded applications with data-level parallelism, a vector processor offers high performance at low power consumption and low design complexity. Unlike superscalar and VLIW designs, a vector processor is scalable and can optimally match specific application requirements.To demonstrate that vector architectures meet the requirements of embedded ...
Christoforos E. Kozyrakis +1 more
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