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Vector Processors for Energy-Efficient Embedded Systems
Proceedings of the Third ACM International Workshop on Many-core Embedded Systems, 2016High-performance embedded processors are frequently designed as arrays of small, in-order scalar cores, even when their workloads exhibit high degrees of data-level parallelism (DLP). We show that these multiple instruction, multiple data (MIMD) systems can be made more efficient by instead directly exploiting DLP using a modern vector architecture. In
Daniel Palmer Dabbelt +5 more
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ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems
2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)Zhaohui Ye
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Floating Vector Processor for Power System Simulation
IEEE Transactions on Power Apparatus and Systems, 1985This paper analyzes microprogram functions of the sparse matrix solution to obtain faster power system simulations such as the power flow calculation and transient stability analysis. The hardware structure and extended instructions of a floating vector processor (FVP) which realize simulation speed up are presented.
M. Takatoo +6 more
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The triangle processor and normal vector shader
ACM SIGGRAPH Computer Graphics, 1988Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated ...
Michael Deering +4 more
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Proceedings SUPERCOMPUTING '90, 2002
The authors report the performance of the 6000-series computers as measured using a set of portable, standard-Fortran, computationally intensive benchmark codes that represent the scientific workload at the Los Alamos National Laboratory. On all but three of the benchmark codes, the 40-ns RISC (reduced instruction set computer) system was able to ...
Margaret L. Simmons, Harvey J. Wasserman
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The authors report the performance of the 6000-series computers as measured using a set of portable, standard-Fortran, computationally intensive benchmark codes that represent the scientific workload at the Los Alamos National Laboratory. On all but three of the benchmark codes, the 40-ns RISC (reduced instruction set computer) system was able to ...
Margaret L. Simmons, Harvey J. Wasserman
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Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System
Proceedings of the the 8th International Virtual Conference on Applied Computing & Information Technology, 2021Recently, the opportunity to use FPGA in the field of embedded computer system has increased. However, the development cost using FPGA is quite high. We can reduce the cost by limiting the development of the dedicated circuit to the essenially required part of the system and by using soft-core processor together.
Yoshiki Kimura +3 more
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Application-specific soft-core vector processor for advanced driver assistance systems
2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. The massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities.
Stephan Nolting +4 more
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, 2019 The hardware landscape is currently changing from homogeneous multi-core systems towards heterogeneous systems with many different computing units, each with their own characteristics.
Johannes Pietrzyk +3 more
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A tridiagonal system solver for distributed memory parallel processors with vector nodes
Journal of Parallel and Distributed Computing, 1991Abstract A variant of the odd-even cyclic reduction algorithm for solving tridiagonal linear systems is presented. Of particular interest is the case where the number of equations is much larger than the number of processors. The target architecture for this scheme is a distributed-memory parallel computer with nodes which are vector processors.
Christopher L. Cox, James A. Knisely
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Time-variant analysis of rotorcraft systems dynamics - An exploitation of vector processors
Journal of Guidance, Control, and Dynamics, 1993In this paper a generalized algorithmic procedure is presented for handling constraints in mechanical transmissions. The latter are treated as multibody systems of interconnected rigid/flexible bodies. The constraint Jacobian matrices are generated automatically and suitably updated in time, depending on the geometrical and kinematical constraint ...
F. M. L. Amirouche +2 more
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