Results 71 to 80 of about 39,832 (274)
CRC 8-bit Encoder-Decoder Component in FPGA using VHDL
Jurnal Elkomika, 2020 AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli.
ANDHI RACHMAN SALEH, SUNNY ARIEF SUDIRO
doaj +1 more source
A C++-embedded Domain-Specific Language for programming the MORA soft processor array [PDF]
, 2010 MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM).
Chalamalasetti, S.R. +3 more
core +1 more source
Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.The wireless communication infrastructure software‐defined radio (SDR) is nowadays essential due to the explosion of digital communication because of its high configurable hardware and software platforms. Several complex signal processing tasks are performed by SDR, and field programmable gate arrays (FPGAs) are the best solution to implement such ...
Achille Ecladore Tchahou Tchendjeu +2 more
wiley +1 more source
Innovative Hardware Accelerator Architecture for FPGA‐Based General‐Purpose RISC Microprocessors
Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.Reconfigurable computing (RC) theory aims to take advantage of the flexibility of general‐purpose processors (GPPs) alongside the performance of application specific integrated circuits (ASICs). Numerous RC architectures have been proposed since the 1960s, but all are struggling to become mainstream.
Ehsan Ali, Iouliia Skliarova
wiley +1 more source
FPGA‐Based Realization of Intelligent Escalator Controller Using Artificial Neural Network
Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.In this work, a proposed intelligent controller has been designed and implemented for a prototype of four stair‐step escalator. The required task of this controller is to manage the supplied power of driving motor of the escalator according to the applied load on the stair‐steps, which is represented by the number of persons standing on the stair‐steps.
Azzad Bader Saeed +3 more
wiley +1 more source
REPRESENTATION IN THE VHDL LANGUAGE OF THE MATRIX ELEMENT MAX [PDF]
, 2023 R.V. Shkirdov
openalex +1 more source
A literature review on V2X communications security: Foundation, solutions, status, and future
IET Communications, Volume 18, Issue 20, Page 1683-1715, December 2024.The article first introduces the development history of the past Internet of Vehicles(IoV), summarizes some common V2X security threats, describes the development and application of the SM commercial algorithm in recent years, and finally, statistics and introduces the part of the development process of the security protocols currently used in IoV ...
Zuobin Ying +3 more
wiley +1 more source
Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code
Jurnal Rekayasa Elektrika, 2012 A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
. Zulfikar
doaj +1 more source
Parametric Macromodels of Differential Drivers and Receivers [PDF]
, 2005 This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient ...
Claudio Siviero +4 more
core +3 more sources
Behavioral modeling of DRACO : a peripheral interface ASIC [PDF]
, 1990 This paper describes the behavioral modeling of DRACO, a peripheral interface Application Specific Integrated Circuit (ASIC) developed by Rockwell International for numerical control applications.
Dutt, Nikil D., Gupta, Rajesh
core