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Serial List Viterbi Decoding with CRC: Managing Errors, Erasures, and Complexity
Global Communications Conference, 2018This paper analyzes the serial list Viterbi algorithm (S-LVA) used in conjunction with optimal CRC codes that minimize probability of undetected error by maximizing the minimum distance between convolutional codewords that pass the CRC check, following ...
Hengjie Yang +2 more
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Fast decoding viterbi algorithm
Proceedings. 2004 International Conference on Information and Communication Technologies: From Theory to Applications, 2004., 2004The fast decoding Viterbi algorithm is proposed in this paper, which depends on majority principle for decision. The proposed algorithm is compared with conventional decoding algorithm. The comparison is done by means of decoder initialization with the metric tableset and the possible states of the encoder calculated.
M. Wainakh, I. Abboud, M. Morhej
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Reconfigurable systolic Viterbi decoder
Gateway to 21st Century Communications Village. VTC 1999-Fall. IEEE VTS 50th Vehicular Technology Conference (Cat. No.99CH36324), 2003This paper introduces a new algorithm which saves the power consumption of the systolic Viterbi decoder. The new algorithm dynamically changes the truncated path length of a Viterbi decoder according to the channel condition, resulting in reduction of power consumption.
K. Takahashi +3 more
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An artificial neural net Viterbi decoder
IEEE Transactions on Communications, 1996The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits.
Wang, Xiaoan, Wicker, Stephen B.
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2008 Fourth International Conference on Natural Computation, 2008
Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest in high-speed applications. A high-speed (2, 1, 6) Viterbi decoder is presented in this paper, which is based on parallel Radix-4 architecture and bit-level carry ...
Qing Li +3 more
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Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest in high-speed applications. A high-speed (2, 1, 6) Viterbi decoder is presented in this paper, which is based on parallel Radix-4 architecture and bit-level carry ...
Qing Li +3 more
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20OMbps Viterbi decoder for UWB
The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005., 2005UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 400 Mbps in full specification mode and 200 Mbps in mandatory mode.
null Sung-Woo Choi, null Sang-Sung Choi
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Low Complexity SST Viterbi Decoder
IEEE Vehicular Technology Conference, 2006Reducing the complexity and power consumption of the Viterbi decoder is one of the important design goals for high throughput wireless systems. Recently, a low complexity decoding algorithm was proposed to reduce the average number of ACS (Add Compare Select) operation of the Viterbi algorithm (VA) using the information of syndrome.
Jin Jie, Chi-ying Tsui
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2021
The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is implemented with a Viterbi decoder. High-speed applications require high-speed Viterbi decoders.
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The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is implemented with a Viterbi decoder. High-speed applications require high-speed Viterbi decoders.
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High performance Viterbi decoder design
Cluster Computing, 2018Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization.
V. Kavitha, S. Mohanraj
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Simulated Viterbi decoding using importance sampling
IEE Proceedings F Communications, Radar and Signal Processing, 1988M.A. Herro, J.M. Nowack
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