Results 161 to 170 of about 131,778 (213)

A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996
used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD’s) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI
H Dawid, G Fettweis, H Meyr
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Feedforward Architectures for Parallel Viterbi Decoding

Journal of VLSI signal processing systems for signal, image and video technology, 1991
The Viterbi-Algorithm (VA) is a common application of dynamic programming. The algorithm contains a nonlinear feedback loop (ACS-feedback, ACS: add-compare-select) which is the bottleneck in high data rate implementations. In this paper we show that, asymptotically, the ACS-feedback no longer has to be processed recursively, i.e., there is no feedback.
Gerhard P. Fettweis, Heinrich Meyr
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An artificial neural net Viterbi decoder

IEEE Transactions on Communications, 1996
The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits.
Xiao-an Wang, Stephen B. Wicker
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Nanophotonic Viterbi decoding

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 2012
An all optical Viterbi decoder on a silicon chip was designed. The device is composed of an optical memory cell and two interfering input arms that use QPSK modulation to encode the incoming bits. The device has a shape of a ring resonator with a size of just a few micrometers and relies on the coupling of modes. Data processing of a few picoseconds is
Ted Frumkin, Amihai Meiri, Zeev Zalevsky
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Memory Management in a Viterbi Decoder

IEEE Transactions on Communications, 1981
Management of the memory contents in a Viterbi decoder is a major design problem for both hardware and software realizations. In a naive implementation, every bit in the memory must be changed (read, modified, and rewritten) for each message bit decoded, and, in addition, some double buffering is required.
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An effective simplifying scheme for viterbi decoder

IEEE 60th Vehicular Technology Conference, 2004. VTC2004-Fall. 2004, 1991
A new reduced-state decoding method is presented. The method constructs state-sets, then classifies, compares, and selects states through certain rules based on a Viterbi algorithm (VA). The decoder complexity is reduced to increasing linearly with constraint-length, as compared to the VA whose complexity increases exponentially with constraint-length.
Peng Zhang, Guangguo Bi, Xiaohu You 0001
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Truncation length for Viterbi decoding

IEEE Transactions on Communications, 1991
A bound is derived and analyzed for the bit error rate (BER) of a Viterbi decoder with survivor truncation. Estimates of the SNR (signal-to-noise ratio) loss on the AWGN (additive white Gaussian noise) channel due to truncation are obtained for convolutional codes. Larger truncation lengths are required than the smallest value that does not effectively
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An efficient adaptive circular Viterbi algorithm for decoding generalized tailbiting convolutional codes

IEEE Transactions on Vehicular Technology, 1994
R V Cox
exaly  

An efficient parallel algorithm for list Viterbi decoding

Signal Processing, 2003
Antonio M Peinado, Victoria Sanchez
exaly  

VITERBI DECODING APPARATUS AND VITERBI DECODING METHOD

2008
WATANABE KOUYA, KAMADA TAKEHIRO
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