Results 181 to 190 of about 2,602 (222)

Efficient scalable architectures for Viterbi decoders

Proceedings of International Conference on Application Specific Array Processors (ASAP '93), 2002
Viterbi decoders (VDs) are widely used today for the decoding of convolutional codes in forward error correction schemes. Efficient deeply pipelined VLSI architectures, the generalized cascade VD and the trellis pipeline-interleaving (TPI) VD are adaptable to a given data rate only to a limited extent.
Stefan Bitterlich, Heinrich Meyr
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A high-throughput reconfigurable Viterbi decoder

2011 International Conference on Wireless Communications and Signal Processing (WCSP), 2011
A reconfigurable Viterbi decoder with high throughput and low complexity is presented in this paper. The proposed Viterbi decoder supports constraint lengths ranging from 3–9, code rates in the range of 1/2–1/3, and arbitrary truncation lengths. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G ...
Rongchun Li, Yong Dou, Jie Zhou 0007, Guo-Qing Lei   +3 more
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Low Complexity SST Viterbi Decoder

IEEE Vehicular Technology Conference, 2006
Reducing the complexity and power consumption of the Viterbi decoder is one of the important design goals for high throughput wireless systems. Recently, a low complexity decoding algorithm was proposed to reduce the average number of ACS (Add Compare Select) operation of the Viterbi algorithm (VA) using the information of syndrome.
Jin Jie, Chi-Ying Tsui
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Design of a super-pipelined Viterbi decoder

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003
This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required.
Lihong Jia, Yonghong Gao, Jouni Isoaho, Hannu Tenhunen   +3 more
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Truncation length for Viterbi decoding

IEEE Transactions on Communications, 1991
A bound is derived and analyzed for the bit error rate (BER) of a Viterbi decoder with survivor truncation. Estimates of the SNR (signal-to-noise ratio) loss on the AWGN (additive white Gaussian noise) channel due to truncation are obtained for convolutional codes. Larger truncation lengths are required than the smallest value that does not effectively
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A dynamically reconfigurable adaptive viterbi decoder

Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02, 2002
The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital communication channels. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy.
Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson   +3 more
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High performance Viterbi decoder design

Cluster Computing, 2018
Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization.
V. Kavitha 0002, S. Mohanraj
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Design and Implementation of Viterbi Decoder with FPGAs

Journal of VLSI signal processing systems for signal, image and video technology, 1999
In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on ...
M. Kivioja, Jouni Isoaho, L. Vänskä
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Viterbi algorithm motives in turbo decoding

IEEE Information Theory Workshop, 2005., 2005
This work addresses the problem of decoding turbo convolutional codes. In particular, it is concerned with the question of how maximum likelihood sequence estimation (MLSE), in the shape of the Viterbi algorithm (VA), can be utilized in the framework of turbo decoding. It is shown that the conventional VA, which is a soft-input hard-output decoder, can
Michael Kerner, Ofer Amrani
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A fully synthesizable parameterized Viterbi decoder

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), 2003
The Viterbi algorithm is widely used in digital communications. It realizes the maximum-likelihood decoding of convolutional codes received from a noisy channel. Depending on the application (terrestrial, digital modems, digital cellular telephone applications and others) a Viterbi decoder must be designed to respect specific requirements such as small
R. Burger, G. Cesana, Maurizio Paolini, Maura Turolla, S. Vercelli   +4 more
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