Results 191 to 200 of about 2,602 (222)

A Reconfigurable Viterbi Decoder for a Communication Platform

2006 International Conference on Field Programmable Logic and Applications, 2006
A new large constraint length, soft decision viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11, and GSM.
Imran Ahmed 0001, Tughrul Arslan
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On the probability of symbol error in Viterbi decoders

IEEE Transactions on Communications, 1997
An upper bound is derived on the probability that at least one of a sequence of B consecutive bits at the output of a Viterbi (1979) decoder is in error. Such a bound is useful for the analysis of concatenated coding schemes employing an outer block code over GF(2/sup B/) (typically a Reed-Solomon (RS) code), an inner convolutional code, and a symbol ...
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Sliding block Viterbi decoders in FPGA

22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
In this paper, we analyze the design of sliding block Viterbi decoders in FPGA based on two proposed parallel Viterbi decoders with different area/performance ratios. Viterbi decoders for two wireless technologies were designed considering the proposed Viterbi decoders achieving reductions in resource utilizations of more than 50% compared to other ...
Mário P. Véstias, Horácio C. Neto, Helena Sarmento   +2 more
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An FPGA Scalable Parallel Viterbi Decoder

2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2018
Viterbi decoders are an essential component in many embedded systems used for decoding streams of N data symbols over noisy channels. The decoding process is a sequential process wherein the decoder builds a trellis for N received symbols and then it traverses the trellis back computing the path in the trellis that implies the minimal amount of ...
Yosi Ben-Asher, Vladislav Tartakovsky, Katrina Portman, Orr Zilberman, Avishi Hadar   +4 more
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A Simple Interleaver for Use with Viterbi Decoding

IEEE Transactions on Communications, 1978
An interleaver/de-interleaver can be used to improve the performance of a Viterbi decoder in the presence of bursty noise. This note describes the design and a method for testing block interleavers which can be used to combat the effects of periodic pulsed RFI.
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A VLSI implementation of a cascade viterbi decoder with traceback

1993 IEEE International Symposium on Circuits and Systems, 2002
A VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read pointer traceback technique. The overall design for a 16-state, rate 1/2-decoder requires about 26,000 transistors and a core area of 8.5 mm/sup 2/ in a 1.2-/spl mu/m two-level metal ...
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton   +9 more
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20OMbps Viterbi decoder for UWB

The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005., 2005
UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 400 Mbps in full specification mode and 200 Mbps in mandatory mode.
null Sung-Woo Choi, null Sang-Sung Choi
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Viterbi Decoder on HF Channels

MILCOM 1986 - IEEE Military Communications Conference: Communications-Computers: Teamed for the 90's, 1986
A new HF modem that relies on Viterbi decoding is described. This software-implemented low to medium rate HF modem incorporates convolutional codes with interleaving and soft Viterbi decoding. Its performance is compared to the theoretical one, as well as to that of an existing, widely used HF modem. It is shown that the interleaved Viterbi decoder and
Joseph M. Perl, Eyal J. Trachtman
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An Asynchronous Viterbi Decoder

2001
Viterbi decoders are used for decoding data encoded using convolutional forward error correcting codes. Such codes are used in a large proportion of digital transmission and digital recording systems because, even when the transmitted signal is subjected to significant noise, the decoder is still able efficiently to determine the most likely ...
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An alternative to metric rescaling in Viterbi decoders

IEEE Transactions on Communications, 1989
In the Viterbi algorithm, the negative log-likelihood estimates, accumulated distances, or path metrics are unboundedly increasing functions of time. For implementation, all variables must be confined to a finite range. The following properties of the Viterbi algorithm can be exploited for this purpose: (1) path selection depends only on differences of
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