Results 61 to 70 of about 9,664,784 (224)
Two Self‐Stabilizing Algorithms for the Maximal Pentagon Partitioning Problem
Concurrency and Computation: Practice and Experience, Volume 38, Issue 19, October 2026.ABSTRACT Given an undirected graph G=(V,E)$$ G=\left(V,E\right) $$, a collection of disjoint subsets of nodes π={V1,…,Vk}(V=V1∪⋯∪Vk)$$ \pi =\left\{{V}_1,\dots, {V}_k\right\}\kern0.3em \left(V={V}_1\cup \cdots \cup {V}_k\right) $$ is called a pentagon partition if each subset Vi(1≤i≤k)$$ {V}_i\kern0.3em \left(1\le i\le k\right) $$ satisfies one of the ...
Tota Yamada +2 more
wiley +1 more source
Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range
IEEE Access, 2016 This paper presents a novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy.
Ibtisam A. Abbas Al-DARKAZLY +1 more
doaj +1 more source
On the Design of a Class of Analog Filters Whose Impulse Response Is a Mittag‐Leffler Function
International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5173-5182, October 2026.Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known forms are summarized in this work. Simulation results using Cadence and experimental results using an FPAA validate the introduced concept. ABSTRACT Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known
Julia Nako +3 more
wiley +1 more source
A VLSI-design of the minimum entropy neuron [PDF]
, 2010 One of the most interesting domains of feedforward networks is the processing of sensor signals. There do exist some networks which extract most of the information by implementing the maximum entropy principle for Gaussian sources.
Brause, Rüdiger W.
core
A CURRENT MIRROR BASED TWO STAGE CMOS CASCODE OP-AMP FOR HIGH FREQUENCY APPLICATION [PDF]
Journal of Engineering Science and Technology, 2017 This paper presents a low power, high slew rate, high gain, ultra wide band two stage CMOS cascode operational amplifier for radio frequency application.
RAMKRISHNA KUNDU +3 more
doaj
Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization
International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5045-5061, October 2026.This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley +1 more source
A Structured Approach to VLSI Layout Design [PDF]
, 1981 A new approach to the VLSI layout problem is proposed that produces a structured floor plan for an arbitrary network of interconnected processing elements.
Krishnan, M. S.
core
Power Minimisation Techniques for Testing Low Power VLSI Circuits (PhD Dissertation)
, 2000 Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register ...
Nicolici, N.
core +1 more source
Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders
International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5140-5147, October 2026.A balanced parallel CPA‐tree architecture with CSLA reduces the critical‐path delay of multi‐operand addition while preserving structural regularity. ASIC results demonstrate delay reductions of up to 34% with low area overhead, providing an efficient and scalable solution for high‐performance arithmetic.
Lucas R. Kieslich +3 more
wiley +1 more source
Algorithmic and Knowledge-based CAD for VLSI
, 1992 The following topics are dealt with: Expert assistance in digital circuit design; use of a theorem prover for transformational synthesis; an overview of high level synthesis technologies for digital ASICs; simulated annealing based synthesis of fast ...
Taylor, Gaynor E.
core +1 more source