Results 71 to 80 of about 13,582,659 (253)
International Journal of Circuit Theory and Applications, Volume 54, Issue 3, Page 1257-1267, March 2026.Proposed active rectifier solution, detailing the high‐side and low‐side power switch control circuit for implementing the active diodes. ABSTRACT This paper proposes a novel active rectifier architecture for wireless power transfer (WPT) systems. In addition to performing rectification, the proposed structure features embedded current monitoring ...
Elisabetta Moisello +3 more
wiley +1 more source
, 2014 Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic
Chandel, Rajeevan +2 more
core +1 more source
Floorplan design of VLSI circuits [PDF]
Algorithmica, 1989 In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules ...
D. F. Wong 0001, C. L. Liu 0001
openaire +1 more source
Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits
Engineering Reports, Volume 8, Issue 3, March 2026.This work begins by outlining the fundamental concepts of MTJs, FinFETs, and the conventional hybrid CMOS/MTJ framework. It then explains the operating mechanism and configuration of the proposed STT‐MTJ/FinFET‐based OR logic gate. The final sections present the simulation outcomes and analyze the influence of FinFET fin variation.
Pillem Ramesh, Atul S. M. Tripathi
wiley +1 more source
Universality for Graphs of Bounded Degeneracy
Random Structures &Algorithms, Volume 68, Issue 2, March 2026.ABSTRACT Given a family ℋ$$ \mathscr{H} $$ of graphs, a graph G$$ G $$ is called ℋ$$ \mathscr{H} $$‐universal if G$$ G $$ contains every graph of ℋ$$ \mathscr{H} $$ as a subgraph. Following the extensive research on universal graphs of small size for bounded‐degree graphs, Alon asked what is the minimum number of edges that a graph must have to be ...
Peter Allen +2 more
wiley +1 more source
Architecture for VLSI design of Reed-Solomon encoders [PDF]
The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that
Liu, K. Y.
core +1 more source
From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula [PDF]
, 2011 © 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions.
Gupta, Navarun +3 more
core
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
VLSI design (Print), 2012 This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit.
Subodh Wairya +2 more
semanticscholar +1 more source
Advanced Biology, Volume 10, Issue 2, February 2026.This is the first study to demonstrate that the e‐transmembrane gut model provides more accurate physiological predictions than conventional cell culture inserts when tested by the dietary compound butyrate. The bioelectronic e‐transmembrane platform integrates technological and biological optimizations, enabling the hosting of a complex human gut in ...
Verena Stoeger +12 more
wiley +1 more source
On testing VLSI chips for the big Viterbi decoder [PDF]
A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing.
Hsu, I. S.
core +1 more source