Results 71 to 80 of about 9,664,784 (224)

Computationally Minimized X-Part for FX Correlator in Big-Data Interferometers

IEEE Access, 2017
Big-data is a challenging domain for high-throughput digital signal processing (DSP), especially in global-projects like the square kilometer array.
Vignesh Raja Balu, S. M. Rezaul Hasan
doaj   +1 more source

An Ultra‐Low‐Power Biopotential Acquisition Analog Front‐End Chip for Wearable Devices

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5030-5044, October 2026.
A 0.8‐V, 1.2‐μW biopotential AFE combines a chopper‐stabilized CCIA with dual‐time‐scale EDO management. The slow DSL preserves > 1 GΩ input impedance, whereas an event‐triggered fast‐recovery path shortens return to the linear range after abrupt electrode‐offset disturbances. ABSTRACT A 0.8‐V, 1.2‐μW biopotential analog front‐end (AFE) IC is presented
Zhang Xin, Yang Tianqi, Xu Wei, Wang Shun, Xiaoxi Ma   +4 more
wiley   +1 more source

VLSI design of a pipelined CORDIC processor [PDF]

In this report we discuss the VLSI realisation of a pipelined CORDIC arithmetic unit to perform stable matrix row operations for the solution of systems of linear equations.
Nudd, G. R., Chown, Paul, Walton, D. W.
core  

A systematic method for configuring VLSI networks of spiking neurons [PDF]

, 2011
Neftci E, Chicca E, Indiveri G, Douglas RJ. A systematic method for configuring VLSI networks of spiking neurons. Neural Computation. 2011;23(10):2457-2497.An increasing number of research groups are developing custom hybrid analog/digital very large ...
Rodney Douglas, Chicca, E, Douglas, R. J., Neftci, E, Indiveri, G., Indiveri, G, Giacomo Indiveri, Elisabetta Chicca, Emre Neftci, Chicca, Elisabetta ; https://orcid.org/, Douglas, R, Neftci, E., Neftci E, Neftci, Emre, Chicca E, Indiveri G, Chicca, Elisabetta, Douglas R, Indiveri, Giacomo, Douglas, Rodney   +19 more
core   +1 more source

A Code‐Invariant QSG–VGA Co‐Design Methodology for Compact CMOS Vector‐Sum Phase Shifters

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5165-5172, October 2026.
A circuit‐level co‐design methodology for compact vector‐sum phase shifters is presented, combining a code‐invariant common‐gate variable‐gain amplifier (VGA) with a resistorless quadrature signal generator (QSG). By maintaining an almost constant input resistance, explicit resistors are eliminated from the QSG.
Uxua Esteban Eraso, Carlos Sánchez‐Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma   +4 more
wiley   +1 more source

Simplified Small‐Signal Modeling Method for Non‐Isolated High Step‐Up Converters

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 4859-4875, October 2026.
A generalized small‐signal modeling methodology for a family of non‐isolated high step‐up DC‐DC converters is proposed. ABSTRACT This work presents a generalized small‐signal modeling methodology for a family of DC–DC converters based on the four‐state switching cell with a wide conversion range (WCR‐4SSC) operating in continuous conduction mode (CCM).
Samuel Antonio Macedo de Oliveira, Pedro Herysson Almeida da Silva, Fernando Lessa Tofoli, Dalton de Araújo Honório   +3 more
wiley   +1 more source

A survey of dynamic power optimization techniques [PDF]

, 2003
One of the most important considerations for the current VLSI/SOC design is power, which can be classified into power analysis and optimization. In this survey, the main concepts of power optimization including the sources and policies are introduced ...
Wang, Xiaojun, Liu, Bin, Weng, Li-Chuan
core   +2 more sources

VLSI design

, 2014
Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets.
Basu, D K
core  

A 0.037 pJ K2$ ext{K}^2$ 338 pW temperature sensor based on dynamic leakage‐suppression logic

Electronics Letters
This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle.
Hao Li, Zhao Yang, Dezhu Kong, Aiguo Yin, Peiyong Zhang   +4 more
doaj   +1 more source

Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model

Journal of Electrical and Computer Engineering, 2015
Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors.
Shupeng Wang, Kai Huang, Tianyi Xie, Xiaolang Yan   +3 more
doaj   +1 more source