Results 81 to 90 of about 9,664,784 (224)
VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT. [PDF]
Sensors (Basel), 2023 Chen SL +8 more
europepmc +1 more source
Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design
IEEE Access, 2014 This paper presents a systematic methodology to develop compact MOSFET models for process variability-aware VLSI circuit design. Process variability in scaled CMOS technologies severely impacts the functionality, yield, and reliability of advanced ...
Samar K. Saha
doaj +1 more source
Reachability Analysis of Sequential Circuits
, 2012 [[abstract]]Reachability analysis is a fundamental technique in the synthesis,verification of VLSI circuits. This paper presents a novel semi-formal approach which combines the advantages of simulation and formal methods to traverse the state space of ...
Jung-Tai Tsai;Chun-Yao Wang;Kuang-Jung Chang
core
Hierarchical Design for VLSI: Problems and Advantages [PDF]
, 1979 This paper describes the hierarchical design process for VLSI circuits and discusses the potential benefits and ...
vanCleemput, W. M.
core
Discover Applied SciencesThis work presents device-to-modelling investigation of a 20 nm double-gate junctionless field-effect transistor (DG-JLFET) with high-k dielectric engineering and artificial neural network (ANN)-based performance prediction.
Siga Karthik +3 more
doaj +1 more source
Bandgap voltage reference design with enhanced tolerance of process variations(增强工艺偏差容忍度的带隙基准电压源设计)
Zhejiang Daxue xuebao. Lixue ban, 2016 随着CMOS工艺特征尺寸的减小，带隙基准电压源在制造过程中因器件失配和工艺波动易导致实际输出电压和目标值发生偏离，降低芯片成品率.为此提出将Pelgrom失配模型引入电路设计中，分别从器件参数、电路结构、版图布局三方面对亚微米级的电路进行工艺偏差优化.基于华润上华(CSMC)0. 5 µm工艺以及Hspice软件仿真，显示基准源输出电压为1.232 54 V，偏差小于5 mV.流片测试结果表明，应用此设计的三通道LED驱动控制芯片成品率达到96.8%，输出电流达到(18±0.5)mA的芯片占99.
YUMiao(俞淼) +3 more
doaj +1 more source
A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS
Active and Passive Electronic Components, 2013 A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay.
Nabihah Ahmad, Rezaul Hasan
doaj +1 more source
A 12 dB 0.7 V 𝟖𝟓𝟎𝝁W CMOS LNA for 866 MHz UHF RFID Reader
Active and Passive Electronic Components, 2010 The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finite 𝑔ds (=1/𝑟0) effect has been
Jie Li, S. M. Rezaul Hasan
doaj +1 more source
A formal verification method: model checking(一种形式化验证方法：模型检验)
Zhejiang Daxue xuebao. Lixue ban, 2006 模型检验作为一种形式化验证方法，近年来在各种硬件、软件设计中得到了广泛应用.文中首先介绍了描述系统行为的Kripke结构和描述系统性质的CTL逻辑，然后介绍了模型检验中常用的两种算法：标记算法和基于固定点的算法，最后介绍了为避免内存爆炸而引入的符号模型检验技术.
YANGJun(杨军) +3 more
doaj +1 more source
Analog VLSI for Robot Path Planning
, 1994 : Analog VLSI provides a convenient and high-performance engine for robot path planning. Laplace's equation is a useful formulation of the path planning problem; however, digital solutions are very expensive.
STAN, MR +9 more
core +1 more source