Results 11 to 20 of about 75,870 (296)

Opportunistic Beamforming in Wireless Network-on-Chip [PDF]

open access: yes2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
Wireless Network-on-Chip (WNoC) has emerged as a promising alternative to conventional interconnect fabrics at the chip scale. Since WNoCs may imply the close integration of antennas, one of the salient challenges in this scenario is the management of coupling and interferences. This paper, instead of combating coupling, aims to take advantage of close
Abadal Cavallé, Sergi   +7 more
openaire   +3 more sources

Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures

open access: yesIEEE Access, 2023
Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures.
Lashmi Kondoth   +3 more
doaj   +1 more source

INTRODUCING A NEW ROUTING ALGORITHM FOR WIRELESS NETWORKS ON CHIP USING REINFORCEMENT LEARNING

open access: yesJordanian Journal of Computers and Information Technology, 2021
Wireless network on chip (WNoC) can be used as an alternative to bus technology in high-core chips in which the multi-hop paths between far apart cores are replaced with a wireless single-hop link.
Zohreh Harati   +3 more
doaj   +1 more source

A remote consultation system for sports injury based on wireless sensor network

open access: yesEAI Endorsed Transactions on Pervasive Health and Technology, 2022
INTRODUCTION: Although current research methods can realize the effective collection of human physiological signals in the health monitoring system, they cannot obtain the ideal detection effect due to the influence of the communication performance in ...
Hongming Guo, Ting Yang
doaj   +1 more source

Congestion-aware wireless network-on-chip for high-speed communication

open access: yesAutomatika, 2020
The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC ...
M. Devanathan   +2 more
doaj   +1 more source

Graphene-enabled Wireless Networks-on-Chip

open access: yes2013 First International Black Sea Conference on Communications and Networking (BlackSeaCom), 2013
Graphene-enabled Wireless Communications (GWC) advocate for the use of graphene-based plasmonic antennas, or graphennas, which take advantage of the plasmonic properties of graphene to radiate electromagnetic waves in the terahertz band (0.1-10 THz). GWC may represent a breakthrough in the research areas of wireless on-chip communications, i.e., among ...
Llatser Martí, Ignacio   +4 more
openaire   +2 more sources

Pulse interspersing in static multipath chip environments for Impulse Radio communications [PDF]

open access: yes, 2016
Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability ...
Abadal Cavallé, Sergi   +5 more
core   +2 more sources

On chip network with increased performance for efficient wireless communication

open access: yesMeasurement: Sensors, 2023
Core systems with network transactions deployed semiconductor materials to develop wireless networks-on-chip to minimize latency with increased performance.
Suresh Ponnan, Tikkireddi Aditya Kumar
doaj   +1 more source

A comprehensive survey of wireless body area networks on PHY, MAC, and network layers solutions [PDF]

open access: yes, 2012
Recent advances in microelectronics and integrated circuits, system-on-chip design, wireless communication and intelligent low-power sensors have allowed the realization of a Wireless Body Area Network (WBAN).
Blondia, Chris   +8 more
core   +2 more sources

Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs

open access: yesМоделирование и анализ информационных систем, 2017
In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj   +1 more source

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