Results 21 to 30 of about 7,349 (255)

Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs

Моделирование и анализ информационных систем, 2017
In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj   +1 more source

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Applied Sciences, 2023
In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research
Yassine Aydi, Sirine Mnejja, Faraqid Q. Mohammed, Mohamed Abid   +3 more
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Hardware-software implementation of the compression and transmission of seismic data [PDF]

E3S Web of Conferences, 2021
A real-time wireless network architecture for seismic data ac-quisition system based on multi-level radio network is proposed. The sin-gle-chip programmable transceiver Si446x that allows creating the first level of the network is considered.
Murtazina Leisan Sh., Danilov Evgeniy V., Ryabchenko Evgeniy Yu., Sherstyukov Oleg N.   +3 more
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Design and analysis of a mesh-based wireless network-on-chip [PDF]

The Journal of Supercomputing, 2012
Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements.
Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh   +2 more
openaire   +3 more sources

Multi-Level Analysis of On-Chip Optical Wireless Links

Applied Sciences, 2019
Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and ...
Franco Fuschini, Marina Barbiroli, Giovanna Calò, Velio Tralli, Gaetano Bellanca, Marco Zoli, Jinous Shafiei Dehkordi, Jacopo Nanni, Badrul Alam, Vincenzo Petruzzelli   +9 more
doaj   +1 more source

Wireless networks-on-chips: architecture, wireless channel, and devices

IEEE Wireless Communications, 2012
Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency.
Matolak, David W, Kodi, Avinash, Kaya, Savas, DiTomaso, Dominic, Laha, Soumyasanta, Rayess, William   +5 more
openaire   +2 more sources

An Analytical Channel Model for Emerging Wireless Networks-on-Chip [PDF]

2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th Intl Symposium on Distributed Computing and Applications for Business Engineering (DCABES), 2016
Recently wireless Networks-on-Chip (WiNoCs) have been proposed to overcome the scalability and performance limitations of traditional multi-hop wired NoC architectures. However, the adaptation of wireless technology for on-chip communication is still in its infancy.
Michael Opoku Agyeman, Quoc-Tuan Vien, Terrence S. T. Mak   +2 more
openaire   +1 more source

An Emergency Monitoring System for Power Cable Tunnels Based on Mobile Wireless Sensor Network

Zhongguo dianli, 2020
To meet the environmental monitoring requirements of power cable tunnels for emergency cases such as communication network being missed, broken-down, or attacked, a low-cost mobile wireless senor network monitoring system was developed based on WiFi and ...
Xinqian XU, Lai XU, Jie CHEN, Yang LIU, Chaopeng ZHANG, Jiahong HE, Bingtuan GAO   +6 more
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On the Cooperative Relaying Strategies for Multi-Core Wireless Network-on-Chip

IEEE Access, 2021
Recently, hybrid wired-wireless Network-on-Chip (WiNoC) has been proposed as a suitable communication fabric to provide scalability and satisfy high performance demands of the exascale era of modern multi/many-core System-on-Chip (SoC) design.
Quoc-Tuan Vien, Michael Opoku Agyeman, Mallik Tatipamula, Huan X. Nguyen   +3 more
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Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

Journal of Low Power Electronics and Applications, 2018
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures ...
Franco Fuschini, Marina Barbiroli, Marco Zoli, Gaetano Bellanca, Giovanna Calò, Paolo Bassi, Vincenzo Petruzzelli   +6 more
doaj   +1 more source