Results 251 to 260 of about 76,193 (289)
Some of the next articles are maybe not open access.
Wireless Network-on-Chip for Multi-Die Systems
2021High performance computing and the need for processing power have cultivated increasing number of on-chip processing elements (PEs), therefore increasing the total overall area. The increase in distance has a negative effect in packet latency, congestion, and total throughput of the system.
Vasil Pano, Baris Taskin
openaire +1 more source
Energy Efficient Transceiver in Wireless Network on Chip Architectures
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs,
CATANIA, Vincenzo +4 more
openaire +2 more sources
2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
openaire +1 more source
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
openaire +1 more source
Performance analysis of wireless 3D network on chip
2012 International Symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012Interconnect infrastructure plays a crucial role in the performance of multi-core systems-on-chip (SoCs). In order to satisfy the continuing demand for energy-efficient and high-performance interconnect fabrics, three-dimensional (3-D) integration, wireless interconnects and other network-on-chip options have been envisioned respectively as compelling ...
Quanyou Feng +4 more
openaire +1 more source
Performance evaluation of wireless networks on chip architectures
2009 10th International Symposium on Quality of Electronic Design, 2009The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned.
Amlan Ganguly +4 more
openaire +1 more source
HiWA: A hierarchical Wireless Network-on-Chip architecture
2014 International Conference on High Performance Computing & Simulation (HPCS), 2014Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged.
Amin Rezaei +3 more
openaire +1 more source
Flow Control Mechanism for Wireless Network-on-Chip
2013 10th International Conference on Information Technology: New Generations, 2013Network on chip (NoC) provides a network-based interconnect infrastructure that facilitates the communications among a slew of function cores in a modern System-on-chip (SoC) design. Apart from topology, switching technique and routing strategy adopted in an NoC, flow control scheme that regulates the packet injection rates is another determining ...
Ling Wang, Zhen Wang, Yingtao Jiang
openaire +1 more source
Kilo-core Wireless Network-on-Chips (NoCs) Architectures
Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution.
Avinash K. Kodi +6 more
openaire +1 more source
Novel Hybrid Wired-Wireless Network-on-Chip Architectures
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015Existing wireless communication interface of Hybrid Wired-Wireless Network-on-Chip (WiNoC) has 3-dimensional free space signal radiation which has high power dissipation and drastically affects the received signal strength. In this paper, we propose a CMOS based 2-dimensional (2-D) waveguide communication fabric that is able to match the channel ...
Michael Opoku Agyeman +5 more
openaire +1 more source
Wireless-assisted multiple network on chip using microring resonators
Microprocessors and Microsystems, 2018Abstract The multiple network-on-Chip (multi-NoC) architecture is an attractive solution to scale on-chip network bandwidth; however, its performance is influenced by its overall communication infrastructure. Incorporating wireless links attract the traffic and cause the power-gated components to stay in sleep state for a longer period of time.
Ali Shahidinejad, Saeed Fathi
openaire +1 more source