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Secure communications in wireless network-on-chips
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017Wireless on-chip communication is an emerging technology that is currently being adopted in order to reduce latency and energy consumption of network transactions in many-core systems. The reason is that the multi-hop nature of conventional electrical network-on-chip has lead to the point of diminishing returns, which even aggravates as the number of ...
Fernando Pereñíguez-Garcia +1 more
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Channel modeling for wireless networks-on-chips
IEEE Communications Magazine, 2013Designing and implementing wireless networks on chips (WiNoCs) presents numerous engineering challenges, in the areas of computer architecture, multiple access, wireless propagation, physical layer communications processing, and device design and fabrication.
Matolak, David W +2 more
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Network on a chip: modeling wireless networks with asynchronous VLSI
IEEE Communications Magazine, 2001We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. The approach is inspired by the remarkable similarity between networks and asynchronous VLSI. Our approach results in simulators that can evaluate network scenarios much faster than real time, enabling a ...
Rajit Manohar, Clinton Kelly IV
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Wireless Network-on-Chip analysis of propagation technique for on-chip communication
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Network-on-Chip (NoC) is a communication paradigm capable of facilitating a scalable interconnection infrastructure for multi core processors. Wireless NoCs have been introduced to improve the communication performance over long-distance processing nodes.
Vasil Pano +4 more
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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A Wireless Network-on-Chip Design for Multicore Platforms
2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011Aggressive scaling of transistors allows integration of hundreds of processors on a chip. However, on-chip interconnects carrying signals between different blocks will be the bottleneck for system performance and reliability. To tackle this problem, we developed an on-chip communication infrastructure based on a network-on-chip architecture and ...
Chifeng Wang +2 more
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Temperature-aware wireless network-on-chip architecture
International Green Computing Conference, 2014Long-range wireless shortcuts in Network-on-Chip (NoC) architectures are shown to significantly improve energy-efficiency in on-chip data transfer. However, over-utilization of the wireless shortcuts and non-uniform traffic patterns may result in thermal hotpots in the NoC links or switches.
Md Shahriar Shamim +4 more
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A Generic On-Chip Debugger for Wireless Sensor Networks
First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), 2006This invited paper overviews the low level debug support hardware required for an on-chip pre-deployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets system-on-chip designs with multiple processor cores.
Andrew B. T. Hopkins +1 more
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Performance evaluation of wireless networks on chip architectures
2009 10th International Symposium on Quality of Electronic Design, 2009The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned.
Amlan Ganguly +4 more
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Flow Control Mechanism for Wireless Network-on-Chip
2013 10th International Conference on Information Technology: New Generations, 2013Network on chip (NoC) provides a network-based interconnect infrastructure that facilitates the communications among a slew of function cores in a modern System-on-chip (SoC) design. Apart from topology, switching technique and routing strategy adopted in an NoC, flow control scheme that regulates the packet injection rates is another determining ...
Ling Wang 0004, Zhen Wang, Yingtao Jiang
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