Results 221 to 230 of about 7,358 (254)

HiWA: A hierarchical Wireless Network-on-Chip architecture

2014 International Conference on High Performance Computing & Simulation (HPCS), 2014
Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged.
Amin Rezaei 0001, Farshad Safaei, Masoud Daneshtalab, Hannu Tenhunen   +3 more
openaire   +1 more source

A novel hierarchical architecture for Wireless Network-on-Chip

Journal of Parallel and Distributed Computing, 2018
Abstract In the architecture of Networks-on-Chip (NoCs), wired structure and multi-hop communications can lead to high power consumption and latency. Wireless NoC (WiNoC) architecture is a new alternative to solve these challenges. In this architecture, long-range wireless links are used instead of multi-hop wired paths.
Bahareh Bahrami, Mohammad Ali Jabraeil Jamali, Shahram Saeidi   +2 more
openaire   +1 more source

Fundamentals of Graphene-Enabled Wireless On-Chip Networking

2017
The book presents the state of art in the emerging field of molecular and nanoscale communication. It gives special attention to fundamental models, and advanced methodologies and tools used in the field. It covers a wide range of applications, e.g. nanomedicine, nanorobot communication, bioremediation and environmental managements.
Abadal Cavallé, Sergi, Llatser Martí, Ignacio, Mestres Sugrañes, Albert, Solé Pareta, Josep, Alarcón Cot, Eduardo José, Cabellos Aparicio, Alberto   +5 more
openaire   +2 more sources

Antennas and Channel Characteristics for Wireless Networks on Chips

Wireless Personal Communications, 2017
We review the current state of the art on antennas for use in wireless networks on chips (WiNoCs) and also provide results on wireless channel characteristics in the WiNoC setting—the latter are largely absent from the literature. We first describe the motivation for constructing these miniature networks, aimed at improving efficiency of future multi ...
William Rayess, David W. Matolak, Savas Kaya, Avinash Karanth Kodi   +3 more
openaire   +1 more source

Energy Efficient Transceiver in Wireless Network on Chip Architectures

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs,
CATANIA, Vincenzo, Mineo A., MONTELEONE, SALVATORE, PALESI, MAURIZIO, PATTI, DAVIDE   +4 more
openaire   +3 more sources

Evaluating the Feasibility of Wireless Networks-on-Chip Enabled by Graphene

Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Peer ...
Abadal Cavallé, Sergi, Mestres Sugrañes, Albert, Iannazzo Soteras, Mario Enrique, Solé Pareta, Josep, Alarcón Cot, Eduardo José, Cabellos Aparicio, Alberto   +5 more
openaire   +1 more source

Hybrid wireless Network on Chip

Proceedings of the 2nd International Workshop on Network on Chip Architectures, 2009
The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. This limitation of conventional NoC architectures can be addressed by introducing long-range, high bandwidth and low power wireless links between the distant ...
Partha Pratim Pande, Amlan Ganguly, Kevin Chang 0002, Christof Teuscher   +3 more
openaire   +1 more source

Complex network-enabled robust wireless network-on-chip architectures

ACM Journal on Emerging Technologies in Computing Systems, 2013
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects.
Paul Wettin, Anuroop Vidapalapati, Amlan Ganguly, Partha Pratim Pande   +3 more
openaire   +1 more source

Wireless network-on-chip: a new era in multi-core chip design

2014 25nd IEEE International Symposium on Rapid System Prototyping, 2014
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange.
Sujay Deb, Hemanta Kumar Mondal
openaire   +1 more source

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient ( $\sim ~1$ pJ/bit) transceivers over extremely short (
Laha, Soumyasanta, Kaya, Savas, Matolak, David W, Rayess, William, DiTomaso, Dominic, Kodi, Avinash   +5 more
openaire   +2 more sources