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On-Chip Wireless Optical Broadcast Interconnection Network
Journal of Lightwave Technology, 2010An on-chip wireless optical broadcast network for future multicore CPU interconnections is introduced in this paper. A baseline topology is composed of 32 identical transmitting/receiving optical dielectric rod antennas arranged around a circular ring.
Hongyu Zhou +4 more
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Channel modeling for wireless networks-on-chips
IEEE Communications Magazine, 2013Designing and implementing wireless networks on chips (WiNoCs) presents numerous engineering challenges, in the areas of computer architecture, multiple access, wireless propagation, physical layer communications processing, and device design and fabrication.
Matolak, David W +2 more
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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Energy Efficient Transceiver in Wireless Network on Chip Architectures
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs,
CATANIA, Vincenzo +4 more
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Wireless Network-on-Chip for Multi-Die Systems
2021High performance computing and the need for processing power have cultivated increasing number of on-chip processing elements (PEs), therefore increasing the total overall area. The increase in distance has a negative effect in packet latency, congestion, and total throughput of the system.
Vasil Pano, Baris Taskin
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Complex network-enabled robust wireless network-on-chip architectures
ACM Journal on Emerging Technologies in Computing Systems, 2013The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects.
Paul Wettin +3 more
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Wireless Network-on-Chip analysis of propagation technique for on-chip communication
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Network-on-Chip (NoC) is a communication paradigm capable of facilitating a scalable interconnection infrastructure for multi core processors. Wireless NoCs have been introduced to improve the communication performance over long-distance processing nodes.
Vasil Pano +4 more
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Performance analysis of wireless 3D network on chip
2012 International Symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012Interconnect infrastructure plays a crucial role in the performance of multi-core systems-on-chip (SoCs). In order to satisfy the continuing demand for energy-efficient and high-performance interconnect fabrics, three-dimensional (3-D) integration, wireless interconnects and other network-on-chip options have been envisioned respectively as compelling ...
Quanyou Feng +4 more
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Performance evaluation of wireless networks on chip architectures
2009 10th International Symposium on Quality of Electronic Design, 2009The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned.
Amlan Ganguly +4 more
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HiWA: A hierarchical Wireless Network-on-Chip architecture
2014 International Conference on High Performance Computing & Simulation (HPCS), 2014Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged.
Amin Rezaei +3 more
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