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HiWA: A hierarchical Wireless Network-on-Chip architecture
2014 International Conference on High Performance Computing & Simulation (HPCS), 2014 Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged.
Amin Rezaei 0001 +3 more
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Optimization Trends for Wireless Network On-Chip
International Journal of Wireless Networks and Broadband Technologies, 2021Designing sustainable and high-performance wireless multi-core chips requires a matchless tradeoff between many aspects including scalable and reliable architectures implementation which in its turn implies aware-wideband energy-efficient wireless interfaces and adopting innovative straightforward optimization approaches to achieve the ...
Saliha Lakhdari, Fateh Boutekkouk
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Approximate Wireless Networks-on-Chip
2018 Conference on Design of Circuits and Integrated Systems (DCIS), 2018Thanks to the forgiving nature of the emerging recognition, mining and synthesis applications, approximate computing (AC) has been recently rediscovered as a viable technique for improving the performance of computing systems. Although the application of AC techniques has, in several cases, an indirect positive effect on the performance of the on-chip ...
Ascia, Giuseppe +5 more
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CDMA Enabled Wireless Network-on-Chip
ACM Journal on Emerging Technologies in Computing Systems, 2014Multihop communication links in conventional Networks-on-Chips (NoCs) results in lower rates of data transfer and higher energy dissipation. Long-range millimeter-wave wireless interconnects were envisioned to alleviate this problem. However, the available bandwidth of the wireless channels is limited and hence an efficient media access control (MAC ...
Vineeth Vijayakumaran +5 more
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Secure communications in wireless network-on-chips
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017Wireless on-chip communication is an emerging technology that is currently being adopted in order to reduce latency and energy consumption of network transactions in many-core systems. The reason is that the multi-hop nature of conventional electrical network-on-chip has lead to the point of diminishing returns, which even aggravates as the number of ...
Fernando Pereñíguez-Garcia +1 more
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Channel modeling for wireless networks-on-chips
IEEE Communications Magazine, 2013Designing and implementing wireless networks on chips (WiNoCs) presents numerous engineering challenges, in the areas of computer architecture, multiple access, wireless propagation, physical layer communications processing, and device design and fabrication.
Matolak, David W +2 more
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Network on a chip: modeling wireless networks with asynchronous VLSI
IEEE Communications Magazine, 2001We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. The approach is inspired by the remarkable similarity between networks and asynchronous VLSI. Our approach results in simulators that can evaluate network scenarios much faster than real time, enabling a ...
Rajit Manohar, Clinton Kelly IV
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Wireless Network-on-Chip analysis of propagation technique for on-chip communication
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Network-on-Chip (NoC) is a communication paradigm capable of facilitating a scalable interconnection infrastructure for multi core processors. Wireless NoCs have been introduced to improve the communication performance over long-distance processing nodes.
Vasil Pano +4 more
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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A Wireless Network-on-Chip Design for Multicore Platforms
2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011Aggressive scaling of transistors allows integration of hundreds of processors on a chip. However, on-chip interconnects carrying signals between different blocks will be the bottleneck for system performance and reliability. To tackle this problem, we developed an on-chip communication infrastructure based on a network-on-chip architecture and ...
Chifeng Wang +2 more
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